Hossein Mashad Nemati

Design of Varactor-Based Tunable Matching Networks for Dynamic Load Modulation of High Power Amplifiers

In this paper, the design of varactor-based tunable matching networks for dynamic load modulation of high power amplifiers (PAs) is presented. Design guidelines to overcome the common breakdown, and tunability problems of the varactors for high power applications are proposed. Based on the guidelines, using commercially available abrupt junction silicon varactors, a tunable matching network is built and measured. The matching network is then used for load modulation of a 1-GHz 7-W class-E LDMOS PA. Static measurements of the load modulated PA show that the power-added efficiency of the PA is improved by an absolute value of 10% at 10-dB backoff. This promising result proves, for the first time, the feasibility of load modulation techniques for high-power applications in the gigahertz frequency range.

Linearization of Efficiency-Optimized Dynamic Load Modulation Transmitter Architectures

In this paper, a detailed linearization procedure for dynamic load modulation (DLM) transmitter architectures is proposed for the first time. Compared with the conventional single-input/single-output digital predistortion (DPD) approach used with traditional power amplifiers (PAs), the proposed linearization scheme is based on a regular memory DPD in combination with an efficiency-optimized static one-to-two mapping inverse model, which constructs the predistorted input signals to the DLM transmitter. The time-alignment issue, which is very important to this dual-input architecture, is also considered. The proposed technique is demonstrated by a 1-GHz 10-W LDMOS PA that employs a varactor-based tunable matching network. A normalized mean square error of -35 dB, and adjacent channel leakage ratio of -43 dBc is achieved, with an average power-added efficiency of 53% for a single-carrier WCDMA signal with 7-dB peak-to-average ratio. Finally, it is shown that the time-alignment sensitivity is relaxed when the proposed linearization scheme is used. This means that the overall complexity of the transmitter implementation can be reduced.

High-Efficiency LDMOS Power-Amplifier Design at 1 GHz Using an Optimized Transistor Model

A 10-W LDMOS harmonically tuned power amplifier at 1 GHz with state-of-the-art power-added efficiency of 80% is presented. The fundamental and second-harmonic load impedances are optimized for maximum efficiency while other harmonics are blocked by a low-pass load network. A simplified model of the transistor specialized for harmonically tuned and switched mode operations is proposed and used for the design. Good agreement between simulations and measurements is observed, indicating high accuracy of the model and design approach for these particular applications.

Design of Highly Efficient Load Modulation Transmitter for Wideband Cellular Applications

In this paper, the high potential of varactor-based dynamic load modulation (DLM) techniques for wideband cellular applications is demonstrated. A systematic design procedure is proposed to ensure high-efficiency wideband performance. It incorporates harmonically tuned power amplifier (PA) concepts and tunable matching techniques in an integrated design. A DLM transmitter at 2.65 GHz with a peak output power of 6 W is designed using the proposed procedure. In order to investigate the wideband performance of the implemented demonstrator, WCDMA signals with scaled bandwidths are employed. The signal peak-to-average ratio is 7 dB and the same for all the experiments. For the 38.4-MHz signal, which has a corresponding channel bandwidth of > 40 MHz, an average power added-efficiency (PAE) of 44%, normalized mean square error (NMSE) of -35 dB, and adjacent channel leakage ratio (ACLR) of -43 dBc are measured.

High Efficiency LDMOS Current Mode Class-D Power amplifier at 1 GHz

A high power, high efficiency current mode class-D (CMCD) power amplifier (PA) is designed, implemented, and characterized based on LDMOS transistors. A drain efficiency of 71% was achieved with an output power of 20.3 W and a gain of 15.1 dB at 1 GHz. To our knowledge, this result represents the highest efficiency for the CMCD PAs based on LDMOS and the highest gain for all switching mode PAs that have been reported for high power applications (output power of more than 7 W), at frequencies above 800 MHz. Moreover, a wide-band lumped-component balun has been used for the CMCD PA which enables significant size reduction of this class of PA for L-band applications

An RF Carrier Bursting System Using Partial Quantization Noise Cancellation

This paper introduces a method for bandpass cancellation of the quantization noise occurring in high efficiency, envelope pulsed transmitter architectures-or carrier bursting. An equivalent complex baseband model of the proposed system, including the -modulator and cancellation signal generation, is developed. Analysis of the baseband model is performed, leading to analytical expressions of the power amplifier drain efficiency, assuming the use of an ideal class B power amplifier. These expressions are further used to study the impact of key system parameters, i.e. the compensation signal variance and clipping probability, on the class B power amplifier drain efficiency and signal-to-noise ratio. The paper concludes with simulations followed by practical measurements in order to validate the functionality of the method and to evaluate the performance-trend predictions made by the theoretical framework in terms of efficiency and spectral purity.

Digital Predistortion for High Efficiency Power Amplifier Architectures Using a Dual-Input Modeling Approach

In this paper, a novel model is proposed for dual-input high efficiency power amplifier (PA) architectures, such as envelope tracking (ET) and varactor-based dynamic load modulation (DLM). Compared to the traditional single-input modeling approach, the proposed model incorporates the baseband supply voltage/load control as an input. This advantage makes the new approach capable to achieve maximized average power-added efficiency (PAE) and minimized output distortion simultaneously. Furthermore, the new approach has shown to be robust towards time misalignment between the RF input and baseband supply voltage/load control signals, and it can be applied with a reduced-bandwidth baseband supply voltage/load control. Experiments have been performed in a varactor-based DLM PA architecture to evaluate the new modeling approach. The results show that it can achieve 9 and 7 dB better performance than the traditional approaches in terms of adjacent channel leakage ratio and normalized mean square error, respectively. At the same time, the average PAE is maximized. Similar results have been achieved with the proposed model even when reduced-bandwidth baseband load control signal is used or time misalignment between the RF and baseband load control input signals exists. Although the new approach is only tested with DLM architecture in this paper, it is very general and can be applied to ET architectures as well.

Characterization of switched mode LDMOS and GaN power amplifiers for optimal use in polar transmitter architectures

In this paper, switched mode power amplifiers classes of operation and device technologies are characterized versus input power and output supply voltage. The results are used to identify optimal control schemes for use in polar transmitter architectures. Then the effects of different control schemes on the requirements for the power amplifier, and the envelope amplifier, as the main building blocks of this architecture, are investigated.

SiC Varactors for Dynamic Load Modulation of High Power Amplifiers

SiC Schottky diode varactors with a high breakdown voltage, a high tuning ratio, and a low series resistance have been designed and fabricated. These characteristics are particularly necessary for the dynamic load modulation of high power amplifiers (PAs), which is an attractive alternative to other efficiency enhancement techniques. For a SiC Schottky diode varactor with a 50- radius fabricated by using a graded doping profile, a breakdown voltage of 40 V, a tuning range of 5.6, and a series resistance of 0.9 were achieved. The results show the great potential of this type of varactors for the use in the dynamic load modulation of high power amplifiers.

Dynamic load modulation of high power amplifiers with varactor-based matching networks

In this paper, the results of dynamic load modulation on a high power amplifier is shown with experiments. A simple static nonlinear model is used as an inverse model, and by dynamically controlling both the input signal to the power amplifier and the load impedance, high efficiency operation of the power amplifier is achieved. The modulated measurements show the feasibility of dynamic load modulation for practical high power, high frequency applications.