Haiying Cao

A Comparative Analysis of the Complexity/Accuracy Tradeoff in Power Amplifier Behavioral Models

A comparative study of state-of-the-art behavioral models for microwave power amplifiers (PAs) is presented in this paper. After establishing a proper definition for accuracy and complexity for PA behavioral models, a short description on various behavioral models is presented. The main focus of this paper is on the modeling accuracy as a function of computational complexity. Data is collected from measurements on two PAs-a general-purpose amplifier and a Doherty PA designed for WiMAX-for different output power levels. The models are characterized in terms of accuracy and complexity for both in-band and out-of-band error. The results show that, among the models studied, the generalized memory polynomial behavioral model has the best tradeoff for accuracy versus complexity for both PAs, and can obtain high performance at half of the computational cost of all other models analyzed.

Design of a Highly Efficient 2–4-GHz Octave Bandwidth GaN-HEMT Power Amplifier

In this paper, the design, implementation, and experimental results of a high-efficiency wideband GaN-HEMT power amplifier are presented. A method based on source-pull/load-pull simulation has been used to find optimum source and load impedances across the bandwidth and then used with a systematic approach to design wideband matching networks. Large-signal measurement results show that, across 1.9-4.3 GHz, 9-11-dB power gain and 57%-72% drain efficiency are obtained while the corresponding power-added efficiency (PAE) is 50%-62%. Moreover, an output power higher than 10 W is maintained over the band. Linearized modulated measurements using a 20-MHz long-term evolution signal with 11.2-dB peak-to-average ratio show an average PAE of 27% and 25%, an adjacent channel leakage ratio of -44 and -42 dBc at 2.5 and 3.5 GHz, respectively.

I/Q Imbalance Compensation Using a Nonlinear Modeling Approach

In-phase/quadrature (I/Q) imbalance is one of the main sources of distortion in RF modulators. In this paper, a dual-input nonlinear model based on a real-valued Volterra series is proposed for compensation of the nonlinear frequency-dependent I/Q imbalance. First, different sources of distortion are identified from experimental measurements, then a dual-input nonlinear I/Q imbalance model is developed. Further, the inverse model is used for I/Q imbalance compensation. Finally, the performance of the I/Q imbalance compensator is evaluated with both simulations and experiments. In comparison with previously published results, the proposed I/Q imbalance compensator shows significantly improved performance. Thus, we prove that a complete nonlinear I/Q imbalance compensation can minimize the effects of the RF modulator in high-performance digital communication systems.

Linearization of Efficiency-Optimized Dynamic Load Modulation Transmitter Architectures

In this paper, a detailed linearization procedure for dynamic load modulation (DLM) transmitter architectures is proposed for the first time. Compared with the conventional single-input/single-output digital predistortion (DPD) approach used with traditional power amplifiers (PAs), the proposed linearization scheme is based on a regular memory DPD in combination with an efficiency-optimized static one-to-two mapping inverse model, which constructs the predistorted input signals to the DLM transmitter. The time-alignment issue, which is very important to this dual-input architecture, is also considered. The proposed technique is demonstrated by a 1-GHz 10-W LDMOS PA that employs a varactor-based tunable matching network. A normalized mean square error of -35 dB, and adjacent channel leakage ratio of -43 dBc is achieved, with an average power-added efficiency of 53% for a single-carrier WCDMA signal with 7-dB peak-to-average ratio. Finally, it is shown that the time-alignment sensitivity is relaxed when the proposed linearization scheme is used. This means that the overall complexity of the transmitter implementation can be reduced.

Design of Highly Efficient Load Modulation Transmitter for Wideband Cellular Applications

In this paper, the high potential of varactor-based dynamic load modulation (DLM) techniques for wideband cellular applications is demonstrated. A systematic design procedure is proposed to ensure high-efficiency wideband performance. It incorporates harmonically tuned power amplifier (PA) concepts and tunable matching techniques in an integrated design. A DLM transmitter at 2.65 GHz with a peak output power of 6 W is designed using the proposed procedure. In order to investigate the wideband performance of the implemented demonstrator, WCDMA signals with scaled bandwidths are employed. The signal peak-to-average ratio is 7 dB and the same for all the experiments. For the 38.4-MHz signal, which has a corresponding channel bandwidth of > 40 MHz, an average power added-efficiency (PAE) of 44%, normalized mean square error (NMSE) of -35 dB, and adjacent channel leakage ratio (ACLR) of -43 dBc are measured.

Digital Predistortion for High Efficiency Power Amplifier Architectures Using a Dual-Input Modeling Approach

In this paper, a novel model is proposed for dual-input high efficiency power amplifier (PA) architectures, such as envelope tracking (ET) and varactor-based dynamic load modulation (DLM). Compared to the traditional single-input modeling approach, the proposed model incorporates the baseband supply voltage/load control as an input. This advantage makes the new approach capable to achieve maximized average power-added efficiency (PAE) and minimized output distortion simultaneously. Furthermore, the new approach has shown to be robust towards time misalignment between the RF input and baseband supply voltage/load control signals, and it can be applied with a reduced-bandwidth baseband supply voltage/load control. Experiments have been performed in a varactor-based DLM PA architecture to evaluate the new modeling approach. The results show that it can achieve 9 and 7 dB better performance than the traditional approaches in terms of adjacent channel leakage ratio and normalized mean square error, respectively. At the same time, the average PAE is maximized. Similar results have been achieved with the proposed model even when reduced-bandwidth baseband load control signal is used or time misalignment between the RF and baseband load control input signals exists. Although the new approach is only tested with DLM architecture in this paper, it is very general and can be applied to ET architectures as well.

Dynamic load modulation of high power amplifiers with varactor-based matching networks

In this paper, the results of dynamic load modulation on a high power amplifier is shown with experiments. A simple static nonlinear model is used as an inverse model, and by dynamically controlling both the input signal to the power amplifier and the load impedance, high efficiency operation of the power amplifier is achieved. The modulated measurements show the feasibility of dynamic load modulation for practical high power, high frequency applications.

Time alignment in a dynamic load modulation transmitter architecture

A time alignment algorithm is proposed for a dynamic load modulation transmitter architecture. The effect of time mismatch between the RF input and baseband control signal is investigated by experiments, and it is shown that unsynchronized signals can result in severe distortion of the output signal. In this paper, cross correlation and sinc interpolation techniques are applied to estimate and compensate for the sub-sample delay between the RF signal path and the baseband control signal path in the measurement system. The performance of the dynamic load modulation transmitter architecture with accurate time alignment is shown by experimental results. The measurement shows that, the efficiency is greatly affected by time alignment and the spectral regrowth is suppressed by more than 10 dB.

A highly efficient 3.5 GHz inverse class-F GaN HEMT power amplifier

This paper presents the design and implementation of an inverse class-F power amplifier (PA) using a high power gallium nitride high electron mobility transistor (GaN HEMT). For a 3.5 GHz continuous wave signal, the measurement results show state-of-the-art power-added efficiency (PAE) of 78%, a drain efficiency of 82%, a gain of 12 dB, and an output power of 12 W. Moreover, over a 300 MHz bandwidth, the PAE and output power are maintained at 60% and 10 W, respectively. Linearized modulated measurements using 20 MHz bandwidth long-term evolution (LTE) signal with 11.5 dB peak-to-average ratio show that 242 dBc adjacent channel power ratio (ACLR) is achieved, with an average PAE of 30%, 247 dBc ACLR with an average PAE of 40% are obtained when using a WCDMA signal with 6.6 dB peak-to-average ratio (PAR).

Comparison of bandwidth reduction schemes in dynamic load modulation power amplifier architectures

This paper compares bandwidth reduction schemes for baseband control signals used in high efficiency power amplifier (PA) architectures, such as envelope tracking and dynamic load modulation (DLM). The baseband control signal used in such architectures usually has 3–4 times wider bandwidth than the modulated radio frequency (RF) signal. Such a wideband signal brings challenges for practical hardware design. In this paper, two bandwidth reduction schemes originally used in envelope tracking are applied on a DLM PA. The performance of both schemes are investigated by simulation. The results show that the bandwidth of the baseband control signal can be effectively reduced from 12.5 MHz to 4 MHz, while at the same time, maintaining a 49% average power-added and acceptable linearity.