Ilias Pappas

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

A simple and continuous polycrystalline silicon thin-film transistor model for SPICE implementation

A simple current-voltage model for polycrystalline silicon thin-film transistors (polysilicon TFTs) is proposed, including the sixth-order polynomial function coefficients fitted to the effective mobility versus gate voltage data, the channel length modulation, and impact ionization effects. The model possesses continuity of current in the transfer characteristics from weak to strong inversion and in the output characteristics throughout the linear and saturation regions of operation. The model parameters are used as input parameters in AIM-SPICE circuit simulator for device modeling. The model has been applied in a number of long and short channel TFTs, and the statistical distributions of the model parameters have been derived which are useful for checking the functionality of TFTs circuits with AIM-SPICE.

Analytical current-voltage model for nanocrystalline silicon thin-film transistors

An analytical model for the drain current above threshold voltage, based on an exponential energy distribution of band tail states, has been applied to bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Analysis of the model shows that the slope of the exponential band tails determines the behavior of the device current-voltage characteristics. Comparison with experimental data shows that few fundamental model parameters, related to the material quality and different physical effects, can be used to describe consistently both output and transfer characteristics of nc-Si TFTs over a wide range of channel lengths.

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

A charge-based compact capacitance model has been developed describing the capacitance-voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward-Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source trans-capacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers.

Electrical transport characterization of nano CMOS devices with ultra-thin silicon film

Regarding short channel GAA, FD-SOI and FinFET MOS devices, we have clearly shown that the mobility is degraded at small gate length, whatever the architecture, the gate stack and the measurement method used. In particular, it has been found that, for FD-SOI, the mobility is more degraded at the top interface than at the bottom interface, indicating that defects are more numerous at the top channel region. The negative role of the nitrogen diffusion from TiN/TaN metal gates has been confirmed revealing a significant reduction of low field mobility with the TiN thickness increase. Low temperature measurements of the mobility have clearly indicated that the scattering processes are strongly modified for short channel devices, which demonstrates that there is an increasing role of channel diffusion scattering centres, most likely neutral point defects, for gate length below 100nm. These extra defects in the channel are likely suspected to be Silicon interstitials injected from the source and drain junction during the S/D implantation process as confirmed by 2D Monte Carlo collision simulations. The concentration and the lateral spatial profile of the generated defects have been implemented into a mobility model that explains reasonably well both the gate length dependence and the temperature variation of the mobility, reinforcing the physical merits of the proposed interpretation for the mobility collapse observed at small channel lengths.

A complete platform and toolset for system implementation on fine-grain reconfigurable hardware

In this paper a complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: the fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. It is the first such complete academic system. The novel energy efficient FPGA architecture was designed and simulated in STM 0.18 mm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block as well as the interconnection network are determined and evaluated for energy, delay and area. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools. q 2004 Elsevier B.V. All rights reserved.

A Fast and Compact Analog Buffer Design for Active Matrix Liquid Crystal Displays Using Polysilicon Thin-Film Transistors

This paper presents a new source-follower type analog buffer for active-matrix liquid crystal displays applications, which exhibits high immunity to the threshold voltage variations of the polysilicon (poly-Si) thin-film transistors (TFTs). The functionality of the buffer was verified through simulations. In order for the simulations to be realistic, parameters extraction from fabricated poly-Si TFTs were used.

A New Analog Buffer Using Low-Temperature Polysilicon Thin-Film Transistors for Active-Matrix Displays

In this paper, a new source-follower-type analog buffer for active-matrix displays, designed by using low-temperature polysilicon thin-film transistors (TFTs), is proposed. The buffer, consisting of five n-type polysilicon TFTs, one bias voltage, and an additional control signal, exhibits high immunity to threshold voltage and mobility variations. The functionality of the proposed buffer was verified by HSPICE simulations. In order to obtain realistic simulations, the TFT model parameters used for the simulations were extracted from fabricated TFTs using the Silvaco tools (ATLAS). The proposed buffer has 7-bit output voltage with the dynamic output voltage range of 7.5 V ranging from 2.5 to 10 V and with resolution up to 0.03 V

An integrated FPGA design framework: custom designed FPGA platform and application mapping toolset development

Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 μm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.