Altaf Hossain

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the synthesis of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). An approach to designing zeroaliasing space compaction hardware in relation to embedded cores-based SOC is proposed in this paper for single stuck-line faults, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) using new graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits, with programs ATALANTA and FSIM.

Further Studies on Zero-Aliasing Space Compression Based on Graph Theory

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the realization of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-onboard to system-on-chip (SOC). This paper revisits the problem of designing zero-aliasing space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing new graph theory concepts, based on optimal generalized sequence mergeability as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximal compaction ratio in the design, along with some experimental results on ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA and FSIM.

Logic fault test simulation environment for IP core-based digital systems

A logic fault test simulation environment for core-based digital systems is proposed in this paper. The simulation environment emulates a typical built-in self-test (BIST) environment with test pattern generator that sends its outputs to a circuit under test (CUT) and the output streams from the CUT are fed into a response data analyzer. The developed simulator is suitable for testing digital IP cores. The paper describes in details the test architecture and application of the logic fault simulator. Some partial simulation results on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided.

Space Compaction for Embedded Cores-Based System-on-Chips (SOCs) Using Fault Graded Output Merger

The design of space-efficient support hardware for built-in self-testing (BIST) is of crucial importance in the design and manufacture of complex system-on-chip (SOC) circuits. This paper reports on a new space compression technique that facilitates designing such circuits using pseudorandom and compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The compaction technique utilizes the concept of fault grading of output lines based on strong and weak compatibility information of output pairs. The proposed technique guarantees simple design with 100% fault coverage for single stuck-line faults, low CPU simulation time, and acceptable area overhead. Simulation runs on ISCAS 85 combinational benchmark circuits with FSIM and ATALANTA programs confirm the usefulness of the suggested approach.

VLSI Circuit Test Vector Compression Technique

A new test vector compression method for VLSI circuit testing is presented in this paper. The technique is essentially software-based, where a program is loaded into the on-chip processor memory along with the compressed test data sets. To reduce the on-chip storage area and testing time, the large volume of test data is first compressed before downloading into the on-chip processor. The proposed method utilizes a set of adaptive coding techniques for achieving lossless compression. The compression program need not be loaded into the embedded processor, as only the decompression of the test data is is necessary for application by the automatic test equipment (ATE). The technique requires minimal hardware overhead, while the on-chip processor core can be reused for normal operation after testing. The feasibility of the developed approach has been demonstrated through extensive simulation experiments on ISCAS 85 and ISCAS 89 benchmark circuits.

Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic

Designing aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper develops an approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input OR/NOR logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.

Cascade of two-input nonlinear logic in designing space compression networks in VLSI

Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, utilizing well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.

Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verification tool

The complexity of modern digital circuits has increased enormously because of paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs). The ensuing intricacy has resulted in a huge challenge in setting up their appropriate fault analysis and testing environment. Though enormous efforts were directed to rapidly test very large-scale integration(VLSI) circuit chips under reasonable cost constraints, with technological advances, new barriers emerged. The subject paper, augmenting earlier works of authors, pertains to developing method that aims to test verify circuit architecture in a hardware-software co-design environment, specifically targeting embedded SOCs. The concept of design-for-testability (DFT) is utilized in this paper, using ModelSim simulation and verification tool, to test simulate the overall design. In earlier works, simulation experience on ISCAS 85 combinational benchmark circuits was provided. In this study, some partial simulation results on ISCAS 89 full scan sequential benchmark circuits are furnished because of space contraint, along with discussion of proposed algorithm and programming basisin a context of ModelSim.

Test vector compression technique in system-on-chip

Some further studies on a hybrid test vector compression technique for VLSI circuits are presented in this paper. In the method proposed herein, the test vectors are first compacted in a hybrid fashion; next, these compressed test vectors are downloaded in the on-chip memory. The decompression software is also loaded in the memory along with test data. The decompression software then decodes the compressed test vectors for testing the specific circuit under test. The current scheme incorporates some new concepts for lossless compression, viz. Burrows-Wheeler transform and associative coder of Buyanovsky transformation. The compression program need not be loaded into the embedded processor, as only the decompression of test data is needed for the automatic test equipment. The developed technique requires minimal memory; besides, the on-chip embedded processor core can be reused for normal operation after testing. The validity of the methodology has been demonstrated through multiple simulation experiments on ISCAS 85 combinational as well as ISCAS 89 sequential benchmark circuits.

Further Studies on Space Compression in Embedded Cores-Based Systems Using Fault Graded Output Merger

The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the synthesis of cores-based system-on-chips (SOCs). This paper reports on further studies on a space compression technique recently developed by the authors that facilitates designing such circuits using pseudorandom and compact test sets, with the basic objective of reducing the storage requirements for the circuit under test (CUT) while still retaining the fault coverage information. The compression technique uses the concept of fault graded output merger based on identifying strong and weak compatibility relations in response data. The proposed method guarantees design with full fault coverage for single stuck-line faults together with low CPU simulation time and acceptable area overhead. Simulation runs on ISCAS 89 full-scan sequential benchmark circuits with ATALANTA and FSIM programs as reported herein confirm once again the usefulness of the suggested approach.