Amirpouya Kavousian

A 192MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28nm CMOS

A low jitter 192MHz crystal reference quadrupler leverages a new active inductor based 48MHz differential XO, two skewed inverters, a new duty cycle correction circuit, and a frequency doubler. The 192MHz quadrupler can serve as a fast, low jitter reference for a low phase noise PLL and requires far less power and area than reference multiplying PLL or MDLL circuits. The measured RMS jitter is 168fs for the XO, and 184fs for 96MHz output (192MHz divide by 2). The entire circuit, including the XO, draws 5.5mA from a 1V supply and occupies 0.045mm2. To our best knowledge, this is the first reference frequency quadrupler with sub-picosecond jitter.

A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS

A 168-fs rms jitter, 48-MHz differential crystal oscillator based on a new active inductor biasing circuit achieves differential operation with low noise, power, and area overhead. This architecture has two significant advantages compared to the single-ended crystal oscillators that are normally used: 1) this circuit rejects power supply noise and interference which leads to lower jitter and 2) the crystal oscillator-induced spurious tones are smaller and therefore less detrimental to sensitive blocks (e.g., LNA) in RF radios. This paper theoretically analyzes the differential crystal oscillator and provides detailed design considerations. A prototype requires half the power and 80% less area than previously reported differential crystal oscillators. Implemented in a 28-nm LP CMOS process, it draws 1.5 mA from a 1-V supply and occupies 0.013 mm2.