Amy W. K. Liu

High performance continuous wave 1.3 μm quantum dot lasers on silicon

We demonstrate record performance 1.3 μm InAs quantum dot lasers grown on silicon by molecular beam epitaxy. Ridge waveguide lasers fabricated from the as-grown material achieve room temperature continuous wave thresholds as low as 16 mA, output powers exceeding 176 mW, and lasing up to 119 °C. P-modulation doping of the active region improves T0 to the range of 100–200 K while maintaining low thresholds and high output powers. Device yield is presented showing repeatable performance across different dies and wafers.

Experimental demonstration of 100nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

Vertical In<inf>0.53</inf>Ga<inf>0.47</inf>As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high I<inf>on</inf>/I<inf>off</inf> ratio (≫10⁴). At V<inf>DS</inf> = 0.75V, a record on-current of 20µA/µm is achieved due to higher tunneling rate in narrow tunnel gap In<inf>0.53</inf>Ga<inf>0.47</inf>As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs.

Experimental Staggered-Source and N+ Pocket-Doped Channel III--V Tunnel Field-Effect Transistors and Their Scalabilities

In this paper, we experimentally demonstrate 100% enhancement in drive current (ION) over In0.53Ga0.47As n-channel homojunction tunnel field-effect transistor (TFET) by replacing In0.53Ga0.47As source with a moderately staggered and lattice-matched GaAs0.5Sb0.5. The enhancement is also compared with In0.53Ga0.47As N+ pocket (δ)-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (λeff) for the double gate, thin-body configuration of the staggered heterojunction and δ-doped channel TFETs. The extracted λeff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

Quantum Dashes on InP Substrate for Broadband Emitter Applications

We report on the development of InAs/InGaAlAs quantum-dash-in-well structure on InP substrate for wideband emitter applications. A spectral width as broad as 58 meV observed from both photoluminescence and surface photovoltage spectroscopy on the sample indicating the formation of highly inhomogeneous InAs-dash structure that results from the quasi-continuous interband transition. The two-section superluminescent diodes (SLDs), with integrated photon absorber slab as lasing suppression section, fabricated on the InAs dash-in-well structure exhibits the close-to-Gaussian emission with a bandwidth (full-width at half-maximum) of up to 140 nm at ~ 1.6 mum peak wavelength. The SLD produces a low spectrum ripple of 0.3 dB and an integrated power of ~ 2 mW measured at 20degC under 8 kA/cm2. The oxide stripe laser exhibits wide lasing wavelength coverage of up to 76 nm at ~ 1.64 mum center wavelength and an output optical power of ~ 400 mW from simultaneous multiple confined states lasing at room temperature. This rule changing broadband lasing signature, different from the conventional interband diode laser, is achieved from the quasi-continuous interband transition formed by the inhomogeneous quantum-dash nanostructure.

Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications

Type II arsenide/antimonide compound semiconductor with highly staggered GaAs<inf>0.35</inf>Sb<inf>0.65</inf>/In<inf>0.7</inf>Ga<inf>0.3</inf>As hetero-junction is used to demonstrate hetero tunnel FET (TFET) with record high drive currents (I<inf>ON</inf>) of 190µA/µm and 100µA/µm at V<inf>DS</inf>=0.75V and 0.3V, respectively (L<inf>G</inf>=150nm). In<inf>x</inf>Ga<inf>1−x</inf>As (x=0.53, 0.7) homo-junction TFETs and GaAs<inf>0.5</inf>Sb<inf>0.5</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As hetero TFET with moderate stagger are also fabricated with the same process flow for benchmarking. Measured and simulated TFET performance is benchmarked with 40nm strained Si MOS-FETs for 300mV logic applications.

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

Staggered tunnel junction (GaAs_0.35Sb_0.65/In_0.7Ga_0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I_on, of 135μA/μm and highest I_on/I_off ratio of 2.7×10⁴ (V_ds=0.5V, V_on-V_off=1.5V). Effective oxide thickness (EOT) scaling (using Al₂O₃/HfO₂ bilayer gate stack) coupled with pulsed I-V measurements (suppressing D_it response) enable demonstration of steeper switching TFET.

Barrier-Engineered Arsenide–Antimonide Heterojunction Tunnel FETs With Enhanced Drive Current

In this letter, we experimentally demonstrate enhancement in drive current <i>I</i>_ON and reduction in drain-induced barrier thinning (DIBT) in arsenide-antimonide staggered-gap heterojunction (hetj) tunnel field-effect transistors (TFETs) by engineering the effective tunneling barrier height Eb_eff from 0.58 to 0.25 eV. Moderate-stagger GaAs_0.4Sb_0.6/In_0.65 Ga_0.35As (Eb_eff = 0.31 eV) and high-stagger GaAs_0.35Sb_0.65/In_0.7Ga_0.3As (Eb_eff = 0.25 eV) hetj TFETs are fabricated, and their electrical results are compared with the In_0.7Ga_0.3As homojunction (homj) TFET (Eb_eff = 0.58 eV). Due to the 57% reduction in Eb_eff, the GaAs_0.35Sb_0.65/In_0.7Ga_0.3As hetj TFET achieves 253% enhancement in <i>I</i>_ON over the In_0.7Ga_0.3As homj TFET at <i>V</i>_DS = 0.5 V and <i>V</i>_GS - <i>V</i>_OFF = 1.5 V. With electrical oxide thickness (Toxe) scaling from 2.3 to 2 nm, the enhancement further increases to 350 %, resulting in a record high <i>I</i>_ON of 135 μA/μm and 65% reduction in DIBT at <i>V</i>_DS = 0.5 V.

Sub-300 nm InGaAs/InP Type-I DHBTs with a 150 nm collector, 30 nm base demonstrating 755 GHz f max and 416 GHz f T

We report InP/InGaAs/InP double heterojunction bipolar transistors (DHBT) fabricated using a simple mesa structure. The devices employ a 30 nm highly doped InGaAs base and a 150 nm InP collector containing an InGaAs/InAlAs superlattice grade. These devices exhibit a maximum f_max = 755 GHz with a 416 GHz /f_T. This is the highest f_max reported for a mesa HBT. Through the use of i-line lithography, the emitter junctions have been scaled from 500-600 nm down to 250-300 nm -all while maintaining similar collector to emitter area ratios. Because of the subsequent reduction to the base spreading resistance underneath the emitter R_b,spread and increased radial heat flow from the narrower junction, significant increases to f_max and reductions in device thermal resistance θ_JA are expected and observed. The HBT current gain β ≈ 24-35, BV_ceo = 4.60 V, BV_cbo = 5.34 V, and the devices operate up to 20 mW / μm² before self-heating is observed to affect the DC characteristics.

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.

Defect assistant band alignment transition from staggered to broken gap in mixed As/Sb tunnel field effect transistor heterostructure

The compositional dependence of effective tunneling barrier height (Ebeff) and defect assisted band alignment transition from staggered gap to broken gap in GaAsSb/InGaAs n-channel tunnel field effect transistor (TFET) structures were demonstrated by x-ray photoelectron spectroscopy (XPS). High-resolution x-ray diffraction measurements revealed that the active layers are internally lattice matched. The evolution of defect properties was evaluated using cross-sectional transmission electron microscopy. The defect density at the source/channel heterointerface was controlled by changing the interface properties during growth. By increasing indium (In) and antimony (Sb) alloy compositions from 65% to 70% in InxGa1−xAs and 60% to 65% in GaAs1−ySby layers, the Ebeff was reduced from 0.30 eV to 0.21 eV, respectively, with the low defect density at the source/channel heterointerface. The transfer characteristics of the fabricated TFET device with an Ebeff of 0.21 eV show 2× improvement in ON-state current compare...