J. M. Fastenau

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (ID) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase ID by more than 20X.

Advanced high-K gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO<inf>x</inf>-2nm InP) in the In<inf>0.7</inf>Ga<inf>0.3</inf>As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t<inf>OXE</inf>) and low gate leakage (J<inf>G</inf>) and (ii) effective carrier confinement and high effective carrier velocity (V<inf>eff</inf>) in the QW channel. The L<inf>G</inf>=75nm In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750µS/µm and high drive current of 0.49mA/µm at V<inf>DS</inf>=0.5V.

Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (LSIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, TQW=10nm) body planar InGaAs device due to (i) narrow fin width (WFIN) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.

Ultrahigh-Speed 0.5 V Supply Voltage

The direct epitaxial growth of ultrahigh-mobility InGaAs/InAlAs quantum-well (QW) device layers onto silicon substrates using metamorphic buffer layers is demonstrated for the first time. In this letter, 80 nm physical gate length depletion-mode InGaAs QW transistors with saturated transconductance gm of 930 muS / mum and fT of 260 GHz at VDS = 0.5 V are achieved on 3.2 mum thick buffers. We expect that compound semiconductor-based advanced QW transistors could become available in the future as very high-speed and ultralow-power device technology for heterogeneous integration with the mainstream silicon CMOS.

\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (LSIDE) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5Å with low JG, and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar TOXE, the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

Quantum-Well Transistors on Silicon Substrate

This paper describes for the first time, the heterogeneous integration of In0.7Ga0.3As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In0.7Ga0.3As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.

Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

In this paper, we experimentally demonstrate 100% enhancement in drive current (ION) over In0.53Ga0.47As n-channel homojunction tunnel field-effect transistor (TFET) by replacing In0.53Ga0.47As source with a moderately staggered and lattice-matched GaAs0.5Sb0.5. The enhancement is also compared with In0.53Ga0.47As N+ pocket (δ)-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (λeff) for the double gate, thin-body configuration of the staggered heterojunction and δ-doped channel TFETs. The extracted λeff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

Heterogeneous integration of enhancement mode in 0.7 ga 0.3 as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

Type II arsenide/antimonide compound semiconductor with highly staggered GaAs<inf>0.35</inf>Sb<inf>0.65</inf>/In<inf>0.7</inf>Ga<inf>0.3</inf>As hetero-junction is used to demonstrate hetero tunnel FET (TFET) with record high drive currents (I<inf>ON</inf>) of 190µA/µm and 100µA/µm at V<inf>DS</inf>=0.75V and 0.3V, respectively (L<inf>G</inf>=150nm). In<inf>x</inf>Ga<inf>1−x</inf>As (x=0.53, 0.7) homo-junction TFETs and GaAs<inf>0.5</inf>Sb<inf>0.5</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As hetero TFET with moderate stagger are also fabricated with the same process flow for benchmarking. Measured and simulated TFET performance is benchmarked with 40nm strained Si MOS-FETs for 300mV logic applications.

Experimental Staggered-Source and N+ Pocket-Doped Channel III--V Tunnel Field-Effect Transistors and Their Scalabilities

Staggered tunnel junction (GaAs_0.35Sb_0.65/In_0.7Ga_0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I_on, of 135μA/μm and highest I_on/I_off ratio of 2.7×10⁴ (V_ds=0.5V, V_on-V_off=1.5V). Effective oxide thickness (EOT) scaling (using Al₂O₃/HfO₂ bilayer gate stack) coupled with pulsed I-V measurements (suppressing D_it response) enable demonstration of steeper switching TFET.

Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications

We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT), fabricated using a mesa structure, exhibiting 282 GHz f/sub /spl tau// and 400 GHz f/sub max/. The DHBT employs a 30 nm InGaAs base with carbon doping graded from 8/spl middot/10/sup 19//cm/sup 3/ to 5/spl middot/10/sup 19//cm/sup 3/, an InP collector, and an InGaAs/InAlAs base-collector superlattice grade, with a total 217 nm collector depletion layer thickness. The low base sheet (580 /spl Omega/) and contact (<10 /spl Omega/-/spl mu/m/sup 2/) resistivities are in part responsible for the high f/sub max/ observed.