Anastasia V. Ulanova

Design of 65 nm CMOS SRAM for Space Applications: a Comparative Study

We study the design of different SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the localization of a strike. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2-μm nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination.

Automatic control system for memory chips performance in a radiation experiment

The paper analyzes the effectiveness of test algorithms of different duration during the functional control of static random access memory (SRAM) during the exposure to total ionizin dose (TID). The results of experimental research SRAM chips using an automated system based on the equipment PXI company National Instruments, justifying the use of the test algorithms such as “MARCH” (long-10N).

Flash memory cells data loss caused by total ionizing dose and heavy ions

The paper provides experimental results of flash memory loss data investigation. Possible mechanisms of charge loss from storage element are reviewed. We provide some guidelines for flash memory evaluation to space application.

Effect of topological placement of memory cells in memory chips on multiplicity of cell upsets from heavy charged particles

An analysis of factors influencing operational reliability of memory chips has been performed. Different topological configurations of 6-transistors memory cells have been considered. Two configurations of cells most sensitive to the influence of multiple cell upsets (MCUs) have been identified.

Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM

The temperature dependence of single-event upset multiplicity in 65 nm CMOS SRAM was investigated in this paper. Experimental results show significant increase of upset multiplicity over a temperature range of 300 to 400 K. Main physical mechanisms leading to the increase of the multiplicity of upsets at elevated temperatures were studied using three-dimensional (3-D) device simulations. A major role of upset voltage decrease and temperature dependence of the parasitic bipolar effect was established. Simulation results can be used for maximal upset multiplicity estimation.

Infrared focal plane array FPA320×256 radiation hardness investigation

Paper discusses influence of proton- and gamma-irradiation on operation of Infrared Focal Plane Array FPA320×256. IR FPA output signal degradation of each pixel vs integration time dependance with uniform illumination (after proton irradiation) and without illumination (after proton as well as gamma irradiation) was considered.

Hardware/software solution for optocouplers with output MOSFET transistors based on National Instruments PXI-platform

The hardware/software solution for measuring parameters of optocouplers with output MOSFET transistors using a PXI-platform and NI Labview software is proposed in the article. As an example, a typical connection circuit for an optocoupler is presented and methods of an input current adjustment using a LED and data received from the TDS-2024 oscilloscope are described.

Verification of SRAM MСUs calculation technique for experiment time optimization

Single Event Upsets are a growing problem in memories. Therefore, it is important to properly characterize them in order to have a clear idea of how they behave in different applications and environments. Experiments using radiation are a usual method to achieve this goal. However, events produced in memories in this way tend to accumulate over time, being difficult to determine the true number of events that have affected the system. In this paper, several experiments have been conducted to validate a technique that allows calculating the number of real events that have been produced after a radiation test.

Advanced system for CMOS SOI test structures measurements

The article considers modernized CMOS SOI test structure measurement system that allows one to control characteristics of both separate transistors and VLSI blocks during experiment. Changes made in hardware and software parts of the measurement setup are discussed and reasoned.

A method for registration of multiple cell upsets in high capacity memory cells induced by single nuclear particles

This study is devoted to the development of a method for the registration of multiple-cell upsets (MCUs) in memory cells induced by single nuclear particles. The presented results illustrate the possibility of finding MCUs in high capacity (higher than 1 Mbit) memory cells using the improved method.