Andre Holfeld

A Fab-Wide APC Sampling Application

In microprocessor manufacturing it is very important to monitor the processed material on certain metrology steps. This is done in order to characterize the manufacturing process by verifying correct processing and ensuring availability of adequate information on the contributors to process variance. In state-of-the-art technologies it has become increasingly challenging to measure all possible and relevant sources of variation. Because low cycle time (manufacturing duration) is of such high importance, it is necessary to minimize the amount of inspection operations/duration on processed material. This paper details the integrated lot-level and wafer-level sampling application deployed in AMDs Fab30 and Fab36, which is capable of providing the means to capture lot, wafer, and event-based sources of variation by best utilizing the available metrology resources. It will also highlight the connection of this application into the areas of advanced-process-control, run-to-run, fault-detection and classification (APC, RtR, FDC).

ACLV degradation: root cause analysis and effective monitoring strategy

Stability of across field line variation (ACLV) is crucial in advanced semiconductor manufacturing. Degraded signatures cause deterioration of transistor parameters and yield loss. After having contained haze issues, the IC industry is now confronting a new reticle degradation mechanism. It has been reported, that targeting energy is changing with the number of exposures and later on a rapid increase of ACLV is observed. Although effective monitoring and correction methods have been introduced, the root cause of this type of reticle degradation has not been fully elucidated. Our AIMSTM, SEM and optical CD measurements on reticle demonstrated consistency with wafer CD measurements and clearly show that pattern distortions on wafers originate from the front side of the reticle. The results indicate the transmission loss to be gradually distributed over the reticle surface causing CD variations. In the most acute case, changes in the center area could be detected by the reticle inspection tool. Dependency of degradation rate on percentage of the clear field on the reticle and reticle type was observed. Finally, using a variety of analytical techniques including AFM, ion and gas chromatography, TOF-SIMS, Auger and TEM we have been able to identify the root cause of this problem. Our experimental results do show that the structural degradation of the absorber film is the primary cause for CD change. Possible mechanisms behind this effect are discussed.

Mask parameter variation in the context of the overall variation budget of an advanced logic wafer Fab

Within our paper we are going to discuss the variation within the patterning process in the context of the overall electrical parameter variation in an advanced logic Fab. The evaluation is based on both the variation of ring oscillators that are distributed across the chip as well as on local variation of matched transistor pairs. Starting with a view back to the 130nm technology, we will show how things and requirements changed over time. In particular we focus on the gate layer where we do a detailed ACLV-comparison from the 130nm technology node down to todays 45nm node. Within the patterning variation we keep special attention on the mask performance. Within that section, we do a detailed wafer-mask correlation analysis. Additionally to the low-MEEF gate layer we show the importance of the mask CD-performance for a typical high MEEF-layer. Finally, we discuss the mask contribution to the overall overlay error for the most critical contact to gate overlay. In all of the cases, we will show that the mask performance is not the limiter within todays most advanced technology, as long as we get access to a world class mask shop.