André Mariano

High-Speed A/D & D/A conversion: A survey

This paper deals with general discussion over high-speed data converter architectures. Nowadays, more and more researches are focused on the ability to design transceivers able to manage digital data as soon as possible right behind the antenna. These so-called Software Defined Radio architectures are one of the easiest ways to design a receiver with low time-to-market impact. Furthermore, most of the recent standards impose either very high frequency ranges, large bandwidth signals and numerous number of bits. Indeed, different topologies of analog-to-digital and digital-to-analog converters are discussed, keeping in mind the very high frequency purpose. To conclude this paper, two designs are presented: a wideband 3-bit 4 Gsps Flash converter and a narrowband 12-bit 4 Gsps Continuous Time Delta-Sigma converter.

Low power and high gain double-balanced mixer dedicated to 77 GHz automotive radar applications

In this paper, we present a mixer implemented in a 130 nm BiCMOS technology dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced Gilbert cell with integrated transformer-based Baluns. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using EM software in order to improve the simulation accuracy. The measurement results of the circuit exhibit a conversion gain and a SSB noise figure of 18.5 dB and 13.8 dB respectively over a 74 to 81 GHz band. Supplied under 2.5 V the power consumption is 80 mW and the ICP1 is −13 dBm. The transformer-based Balun allows a good input matching at the RF input port over a 16 GHz range from 72 to 88 GHz.

High-speed CMOS analog-to-digital converter for front-end receiver applications

Modern front-end receivers perform direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The final aspiration is to directly digitize the RF signal and hence eliminate any RF/analog mixers. In order to direct digitize the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these specifications, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) to be used as a quantizer in modern digital receivers. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sample rate in a 0.8-2GHz bandwidth.

Continuous-Time Delta-Sigma Modulator based on High-Speed Low-Resolution A/D Converter

This paper presents an advanced design methodology using a combination of behavioral models and transistor level models. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. In order to validate the proposed methodology, a continuous-time delta-sigma modulator based on a high-speed low-resolution analog-to-digital converter is modeled. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front-end receivers.

4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversion

We present in this article a fourth-order integrated LC bandpass Delta-Sigma modulator for direct conversion of high intermediate frequencies. It is designed in a 0.25 μm BiCMOS SiGe:C process from STMicroelectronics. The modulator is able to direct digitize a 1GHz IF signal in a 20MHz bandwidth. The continuous-time loop filter employs two integrated LC resonators with active Q?enhancement circuits. A multi-feedback architecture is used to achieve higher order noise-shaping, while maintaining the modulator stability. A multibit quantizer was implemented to reduce quantization noise and improve stability.

60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies

This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.

A low power and high gain double-balanced active mixer with integrated transformer-based Baluns dedicated to 77 GHz automotive radar applications

In this paper, we present a low power and high gain mixer dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced active Gilbert cell with integrated transformer-based Baluns. These Baluns allow converting the single-ended input signals to differential with an amplitude and phase imbalance of 0.3 dB and 179°, respectively. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using HFSS simulator in order to improve the simulation accuracy. The proposed mixer consumes 105 mW and achieves 16.4 dB of conversion gain and 13.2 dB of noise figure.

A mixed-signal Built-In Self-Calibrated Time-Interleaved ADC in 65nm CMOS technology

Analog-to-Digital (A/D) conversion is faced with strong requirements in terms of resolution and frequency. Time-Interleaved Analog-to-Digital Converters (TIADC) are popular because they offer a higher sampling frequency. But, their architecture introduces errors that affect the resolution of conversion. This paper presents a built-in method of calibration dedicated to TIADC. Mixed-simulations are performed merging transistor-level in 65nm CMOS technology and behavioral blocks in VHDL-AMS language to validate the feasibility of a Built-In Self-Calibration (BISC) system which corrects offset, gain and timing error. Technological constraints of the analog part of the BISC circuitry are highlighted. An orthogonal calibration is applied in a 4-ADC TIADC system and a detailed choice of the methodology is described.

Design of High Sensitivity Radiofrequency Energy Harvesters Dedicated to Low-Power Applications

The Radiofrequency (RF) energy harvesting is a widespread technique to extend the lifetime of devices in low power applications such as Wireless Sensor Networks (WSNs). This paper presents the comparison between a n-stage traditional CMOS voltage multiplier and a n-stage voltage multiplier using bulk biasing to overcome the threshold voltage drop. The two rectifiers operate at 900 MHz ISM band and are prototyped using a standard CMOS 130 nm process. The rectifier circuits were placed into a quad flat no leads (QFN) package and mounted on a standard FR4 board with commercially available devices. The bulk-biased rectifier achieves a significant increase in power efficiency and low voltage-drop. Loaded by a 400 kΩ resistor, typically 3.6 μW/1.2 V, the power efficiency reaches 58%, which is an improvement of about 50% compared with the traditional circuit. Concerning the RF energy harvesters, they are able to deliver an output voltage of 1 V at approximately 900 MHz requiring an available input power of –25.5 dBm and –23 dBm using the bulk-biased and traditional architectures, respectively. Furthermore, the harvesters operate at 3 meters delivering an output power of 1 μW when a power source radiates 19 and 20.5 dBm EIRP, for bulk-biased and traditional circuit, respectively.

Accurate multi-bit feedback DAC dedicated to high-speed Continuous-time ΔΣ converters

This paper presents the behavioral modeling and circuit design of an accurate multi-bit DAC dedicated to high-speed Continuous-time ΔΣ converters. The multi-bit DAC element mismatch is modeled, demonstrating that the non-linearities coming from the feedback DACs is awful for Continuous-time ΔΣ modulators. The proposed DAC is dimensioned in order to achieve best matching, reaching an unit current source relative standard deviation up to 0.7%. A full high-speed Continuous-time ΔΣ converter is implemented using the accurate DAC, achieving a SNR of 76 dB in a widebandwidth of 20 MHz.