Cédric Majek

Characterization and Modeling of Graphene Transistor Low-Frequency Noise

This brief presents low-frequency noise measurements on a graphene field-effect transistor with graphene layer decomposed from SiC substrate. The measurements indicate the predominance of flicker noise in the current noise source measured between drain and source with quadratic dependence with a drain current. The noise level is inversely proportional to the channel area indicating the location of the main noise source to be in graphene layer. From these measurements, the main noise sources, including the main flicker noise and the Johnson noise contributions, have been introduced in a compact model. This compact model has been built using dc characterization results. Finally, the noise compact model has been validated through comparison to noise measurement.

The factorial Delay Locked Loop: a solution to fulfill multistandard RF synthesizer requirements

This paper presents the study of a frequency synthesizer dedicated to multistandard wireless objects: the factorial delay locked loop (DLL). Feasibility of such a circuit has been already made, according to behavioral simulations, but no investigation was performed on the ability of the system to take into account all the requirements of multistandard frequency synthesizer, and particularly, the phase noise response of the system.

A programmable CMOS RF frequency synthesizer for multi-standard wireless applications

This paper deals with a new frequency synthesizer dedicated to multi-standard wireless applications. It converts a 50 MHz wave clock into two outputs in quadrature phase. It takes advantage of the DLL topology in terms of jitter and phase noise and has no external element. Simulations of the structure designed with a 130 nm SOI CMOS technology confirming the performance of the system are also presented.

Optimized Ring Oscillator With 1.65-ps Gate Delay in a SiGe:C HBT Technology

In this letter, we report a record gate delay of 1.65 ps of a current-mode logic ring oscillator (RO) fabricated with an advanced SiGe:C heterojunction bipolar transistor technology. Outstanding performance has been achieved through process and layout optimization and inductive peaking in series with the load resistor. The RO operates at a single-ended voltage swing of 200 mV. The transistors used in the RO exhibit a peak transit frequency fT of 310 GHz and a peak maximum oscillation frequency fmax of 400 GHz. To the best of our knowledge, a gate delay of 1.65 ps is the fastest result for a bipolar transistor-based technology.

Low power and high gain double-balanced mixer dedicated to 77 GHz automotive radar applications

In this paper, we present a mixer implemented in a 130 nm BiCMOS technology dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced Gilbert cell with integrated transformer-based Baluns. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using EM software in order to improve the simulation accuracy. The measurement results of the circuit exhibit a conversion gain and a SSB noise figure of 18.5 dB and 13.8 dB respectively over a 74 to 81 GHz band. Supplied under 2.5 V the power consumption is 80 mW and the ICP1 is −13 dBm. The transformer-based Balun allows a good input matching at the RF input port over a 16 GHz range from 72 to 88 GHz.

A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture

A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of the both architecture and more particular to the non-accumulation of random timing jitter. On the other hand, such a methodology could relax constraints on the loop filter and it would then be possible to increase the architecture bandwidth without taking care of stability drawbacks. By the way, the settling time could be largely improved.

On the use of body biasing to control gain, linearity, and noise figure of a mm-wave CMOS LNA

In this paper, the use of body biasing to control gain, linearity, and noise figure in CMOS low-noise amplifiers (LNAs) is investigated. As a proof of concept, a 60-GHz 4-stage cascode CMOS variable-gain LNA is designed and laid out in a 6 5nm CMOS technology. To improve the accuracy of the post-layout simulations, all inductors are modeled and simulated with a 3-dimentional electromagnetic solver. Post-layout simulation results show that the LNA achieves a maximum gain of 23.5 dB at 60 GHz while consuming 38 mW from a 1.2-V supply. By changing the body bias voltage of the transistors in the two intermediate stages, the overall gain varies from 13 to 23.5 dB providing more than 10 dB of gain range. Adjusting the body biasing of the transistors in the first and last stage, respectively, results in a minimum noise figure of 6.5 dB at 60 G Hz and the maximum IIP3 of more than +1dBm for the overall amplifier.

60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies

This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.

A digitally tuned Voltage Controlled Delay Element for 1-10GHz DLL-based frequency synthesis

This paper presents an original topology for Voltage Controlled Delay Element used in a DLL-based oscillator. This cell works from 1 to 10GHz achieving the phase noise performances required for the targeted wireless standards. The current consumption is lower than 9mA under 1V supply voltage. Thanks to the new topology a delay bank control scheme is feasible, paving the way to digitally controlled DLL.

A low power and high gain double-balanced active mixer with integrated transformer-based Baluns dedicated to 77 GHz automotive radar applications

In this paper, we present a low power and high gain mixer dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced active Gilbert cell with integrated transformer-based Baluns. These Baluns allow converting the single-ended input signals to differential with an amplitude and phase imbalance of 0.3 dB and 179°, respectively. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using HFSS simulator in order to improve the simulation accuracy. The proposed mixer consumes 105 mW and achieves 16.4 dB of conversion gain and 13.2 dB of noise figure.