Bernardo Leite

An Analytical Broadband Model for Millimeter-Wave Transformers in Silicon Technologies

A lumped element model to represent the behavior of millimeter-wave (mm-wave) integrated transformers is presented. Details on the topology allowing efficient mm-wave operation are given. The model presents a 2- π architecture and contains the equations to evaluate its components values. These equations depend on both technological and geometric characteristics of the transformer. The model is validated through experimental data of a set of 65-nm CMOS and 130-nm BiCMOS transformers. A very close agreement is shown for both S-parameter and inductance values up to 110 GHz.

Shielding structures for millimeter-wave integrated transformers

Shielding structures intended to improve the performance of millimeter-wave transformers are presented. The loss mechanisms of the components are discussed and the losses related to the silicon substrate are shown to be the most relevant. A patterned ground shield and a floating shield are detailed and their influences in terms of inductance, quality-factors, coupling coefficients and minimum insertion loss are evaluated through measurement and electromagnetic simulations. Results indicate that quality-factors are deteriorated by the use of patterned ground shields, whereas the use of floating shields allows a slight improvement without degrading other characteristics of the transformer.

A 27.5-dBm linear reconfigurable CMOS power amplifier for 3GPP LTE applications

In this paper, a reconfigurable power amplifier (PA) fully integrated in 65-nm CMOS technology, combining Envelope Tracking (ET) and Power Transistor Switching (PTS) techniques, and robust to battery depletion is presented. The main objective of the proposed architecture is to significantly improve the average efficiency in comparison with a stand-alone power amplifier at power back-off. A distributed active transformer (DAT) is also implemented to recombine power generated by the parallelized power cells which can be turned on/off in response to the desired output power. Simulations were conducted in the 3GPP LTE band at 2.535GHz to validate the proposed implementation. Results show that the proposed topology provides higher power added efficiency (PAE) and reduced current consumption at power back-off compared to a stand-alone PA. The most significant improvement is obtained at 9 dB back-off from 27.5dBm where PAE is improved by 8%.

Design and characterization of CMOS millimeter-wave transformers

A comprehensive analysis of the impact of geometric parameters on the design of millimeter-wave integrated transformers is presented. Transformers presenting the same stacked topology but different diameters and trace widths were fabricated in a 65 nm CMOS technology and their performance was compared in terms of inductance, quality-factors, coupling coefficient and minimum insertion loss. Results of electromagnetic simulation and measurement are exposed, showing an excellent agreement in a wide frequency band. It is observed that transformers with different diameters present similar performances but different resonance frequencies, whereas transformers with wider traces can present better minimum insertion loss results.

Low power and high gain double-balanced mixer dedicated to 77 GHz automotive radar applications

In this paper, we present a mixer implemented in a 130 nm BiCMOS technology dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced Gilbert cell with integrated transformer-based Baluns. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using EM software in order to improve the simulation accuracy. The measurement results of the circuit exhibit a conversion gain and a SSB noise figure of 18.5 dB and 13.8 dB respectively over a 74 to 81 GHz band. Supplied under 2.5 V the power consumption is 80 mW and the ICP1 is −13 dBm. The transformer-based Balun allows a good input matching at the RF input port over a 16 GHz range from 72 to 88 GHz.

Optimization of 65nm CMOS passive devices to design a 16 dBm-P sat 60 GHz power amplifier

The optimization of passive devices is performed to contribute to the design of a linear 60 GHz Power Amplifier (PA). The difficulty in this design consists in the use of thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors dedicated for pure digital applications. In this context, compact inductors and Transmission lines (T-lines) are analyzed, measured and compared at millimeter-Wave (mmW) frequencies. Moreover, a technique of Common Mode Rejection Ration (CMRR) improvement applied for baluns is presented and validated with measurements. A Parallel PA that combines 8 high-efficiency unit power cells is designed using 65nm CMOS technology from STMicroelectronics. The experimental results show a saturated output power (Psat) of 16 dBm with a 14 dBm 1dB-output compression point (OCP1dB).

Optimized power combining technique to design a 20dB gain, 13.5dBm OCP1 60GHz power amplifier using 65nm CMOS technology

Millimeter-wave Distributed Active Transformer (DAT), baluns and zero degree 1-4 splitter have been optimized to design a 60 GHz parallel Power Amplifier (PA). The implementation is based on a thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors in 65 nm CMOS technology from STMicroelectronics. A lumped model based analysis is presented to compare pure voltage and mixed voltage and current combining techniques. Simulated and measured results are reported. At 61 GHz, the PA achieves a peak power gain of 20 dB with a 13.5 dBm 1dB-output compression point (OCP1dB), 15.6 dBm output power and a Power Added Efficiency (PAE) of 6.6% from a 1.2 V supply. To the authors knowledge, these results represent the highest linear output power and gain performances among PAs using the same technology.

A low power and high gain double-balanced active mixer with integrated transformer-based Baluns dedicated to 77 GHz automotive radar applications

In this paper, we present a low power and high gain mixer dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced active Gilbert cell with integrated transformer-based Baluns. These Baluns allow converting the single-ended input signals to differential with an amplitude and phase imbalance of 0.3 dB and 179°, respectively. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using HFSS simulator in order to improve the simulation accuracy. The proposed mixer consumes 105 mW and achieves 16.4 dB of conversion gain and 13.2 dB of noise figure.

65 GHz CMOS-SOI low power consumption voltage controlled oscillator

This paper presents a 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65nm CMOS SOI process. The proposed VCO achieves a frequency tuning range (FTR) of some 9.7% and a phase noise of -111 dBc/Hz at 10 MHz of the carrier. The power consumption is 1.1 mW when biased with a 0.8 V power supply. The silicon footprint of the VCO core is only 0.047 mm2.