Andrei Shibkov

ESD Network Design Principles

This chapter covers material needed for understanding the next level of the ESD design hierarchy – the protection network. The protection network or protection circuit is usually composed of ESD protection clamps (cells) connected together in a way that provides a high current path for all of the pin-to-pin combinations. This network is engineered based on certain general principles and assumptions that are discussed below.

On chip ESD protection of 600V voltage node

This study presents for the first time ESD protection solutions in integrated silicon process technologies for the voltage range up to 600V. The ESD protection clamp is implemented using a NLDMOS-SCR type ESD device architecture. The study presents both reversible triggering I-V characteristics suitable for package level ESD protection as well as dependence of the ESD device characteristics upon the structure parameters and the state of a control electrode.

Active clamps with hybrid BJT-CMOS operation mode

A method to exploit the internal gain of the parasitic bipolar transistor in integrated LDMOS devices achieving a mixed bipolar-CMOS regime is proposed and validated using numerical simulation and experimental results. An improvement of active protection clamps in ESD component, HMM, and surge operation regime is demonstrated. The same principle for NLDMOS device in mixed bipolar-CMOS in linear regime is further demonstrated and applied for power stages.

Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes

Abstract This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data.

PMOS arrays self-protection capability limitation

A study of PMOS arrays self-protection capability, related HBM-TLP miscorrelation and HBM passing level windowing effect is presented. Based on experimental results and 2D mixed-mode numerical simulation analysis the physical mechanism of the PMOS self-protection limitation is determined to be a complex two-stage phenomenon. It is initiated by a “weak” isothermal avalanche-injection conductivity modulation followed by electro-thermal spatial current instability in the 1μs time domain due to the positive feedback between thermal carrier generation and local power dissipation. The follow-up measures to improve the PMOS array self-protection capability are discussed and validated.

System-Level and Discrete Components ESD

This final chapter presents material on a rather cross-disciplinary subject related to system-level ESD robustness. System-level ESD requirements are defined by different standards and specifications than component-level ESD requirements. Component-level ESD standards are specified to ensure ESD robustness of the integrated circuits and components during manufacturing and handling inside the controlled, protected ESD environment until the components are incorporated into the system. ESD specifications on the component level are circuit specific and package specific, practically until the component is mounted on the print circuit board. It is expected that when the component is mounted in the properly designed system, the system’s design will guarantee the absence of events that result in stress of the components above the absolute maximum limits, even when the system itself experiences an ESD event.

Standard and ESD Devices in Integrated Process Technologies

In Chapter 2, conductivity modulation mechanisms were discussed based upon examples of these mechanisms in corresponding elementary semiconductor structures. The purpose of Chapter 3 is to describe how these conductivity modulation phenomena are realized in both standard devices supported by electrical design rules of given integrated process technology and free ESD devices developed in the process.

Cross-Domain interaction at system level stress

A scenario of unexpected failures of low voltage analog domains at system level stress has been studied both experimentally using test structures and through mixed-mode numerical simulation. The analysis of the failure mechanism and validated design fix measures are presented.

Low voltage SCR clamp with high-V T reference

An advanced solution for local protection of the <;2V analog input pins is proposed. It is based on LVTSCR and a simple driver circuit with high threshold voltage reference CMOS structure. According to experimental TLP characteristics and mixed-mode simulation analysis for 90 nm analog power process the new clamp provides low clamping voltage waveforms and reduced leakage current.

ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package

Adding low-cost front-end processing to a passive interposer process flow enables the low-cost processing of diodes, SCRs and bipolar transistors. Using those devices in an ESD protection design allows moving a large part of the ESD protection from the stacked die to the interposer.