Griselda Bonilla

Electromigration in Cu(Al) and Cu(Mn) damascene lines

The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only alloy lines. These results indicated that the existence of bamboo grains in bamboo-polycrystalline lines played a critical role in slowing down the EM-induced void growth rate. The bamboo grains act as Cu diffusion blocking boundaries for grain boundary mass flow, thus generating a mechanical stress-induced back flow counterbalancing the EM force, which is the equality known as the “Blech short length effect.”The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only al...

Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio.

Low-field TDDB reliability data to enable accurate lifetime predictions

A 30 month module-based low-field TDDB study of 90nm pitch Back End of the Line (BEOL) interconnect structures and a 9 month study of 80nm pitch BEOL structures have shown that the commonly used root-E extrapolation model is overly conservative at predicting TDDB lifetimes at low applied fields. A less conservative acceleration model is required to make accurate lifetime predictions at low fields.

Reliability challenges for the 10nm node and beyond

Technology elements for the 10nm node and beyond include FINFETs on bulk or SOI, replacement gate process, multi-workfunction gate stacks, self-aligned contacts, and alternative channel materials. This paper describes current trends and how improved physics understanding and models can enable us to anticipate the effects of scaling on reliability even in early stages of development.

Experimental Determination of the Toughness of Crack Stop Structures

In this paper we present an experimental approach to the determining the toughness of crackstop structures. It is shown that methods used for adhesion testing can be adapted to quantitatively determine the effective toughness of different crackstop designs. A design based on metal pad shapes connected together with vias is shown to be capable of producing toughnesses that are 3.75 times the intrinsic toughness of the dielectric. In an optimized design we obtain a further 60% improvement in the crackstop toughness. The experiments presented provide an accurate way of determining the effectiveness of crackstop designs in arresting dicing flaws driven by the stresses present in different packages.

Delayed mechanical failure of the under-bump interconnects by bump shearing

Packaging-induced stresses can cause mechanical failures of various forms in the Cu/low-k interconnects. Here we report a time-dependent failure mode of the interconnects underneath the copper pillar bump. Delayed catastrophic fracture is observed in the interconnect dielectrics when a sustained shear load is applied on the bump using a single bump shear setup. The time to failure is found to be highly sensitive to the load level and temperature, but not to the environmental humidity. However, moisture diffusion through intentionally broken moisture seal can accelerate the failure process. Quantitative analysis suggests the delayed failure can be well captured over a wide range of testing conditions by a model based on subcritical crack growth in the interconnect dielectrics.

Effect Of Impurity On Cu Electromigration

The impact of the existence of Cu grain boundaries on the degradation of Cu interconnect lifetime at the 45 nm technology node and beyond has suggested that improved electromigra‐tion in Cu grain boundaries has become increasingly important. In this paper, solute effects of non‐metallic (C, Cl, O and S) and metallic (Al, Co, In, Mg, Sn, and Ti) impurities on Cu elec‐tromigration were investigated. The Cu alloy interconnects were fabricated by adjusting Cu electroplating solutions or by depositing a Cu alloy seed, a thin film layer of impurity, an alloy liner, or a metal cap. A large variation of Cu grain structure in the samples was achieved by adjusting the wafer fabrication process steps. The non‐metallic impurities were found to be less than 0.1% in the electroplated Cu with no effect on Cu electromigration lifetimes. Most of the metallic impurities reduced Cu interface and grain boundary mass flows and enhanced Cu lifetime, but Al, Co, and Mg impurities did not mitigate Cu grain boundary diffusion.

Line Resistance and Electromigration Variations Induced by Hydrogen-Based Plasma Modifications to the Silicon Carbonitride/Copper Interface

This paper reports a detailed study of several hydrogen-based plasma cleans prior to plasma-enhanced chemical vapor deposition of silicon carbonitride cap films, and it finds a tradeoff between improved electromigration and increased copper resistivity. Previously proposed mechanisms do not explain this tradeoff, and we propose an alternative mechanism for the cap/copper interface modification. Electromigration is improved by forming a copper silicide interfacial layer, but the copper resistivity is also increased by silicon diffusion into the copper from the cap/copper interface. Hydrogen-based plasmas generate silicon by reacting with the silicon nitride seasoning layer on the chamber surfaces and transporting the silicon to the copper surface. The transport of silicon can be prevented by adding nitrogen to the plasma or removing the seasoning layer.

On the contribution of line-edge roughness to intralevel TDDB lifetime in low-k dielectrics

A TDDB reliability experiment was performed on interdigitated comb structures with intentionally severe line-edge roughness and the results were then compared to a simple theoretical model. It is seen that for the case studied, the predictions of the model do not compare well to the experimental data, but that for some observed cases the effect of reducing spacing between lines is so strong that more substantial defects must be invoked as a source of failure.

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.