Naftali E. Lustig

Gate dielectric and contact effects in hydrogenated amorphous silicon‐silicon nitride thin‐film transistors

The characteristics of glow‐discharge hydrogenated amorphous silicon‐silicon nitride (a‐Si:H/a‐SiNx:H) thin‐film transistors (TFTs) are reported for various deposition conditions. TFTs incorporating a N‐rich nitride gate dielectric, a‐SiN1.6:H, are superior to a‐Si:H TFTs with a Si‐rich gate nitride, a‐SiN1.2:H. In particular, the N‐rich gate nitride TFTs show considerably less interface or near‐interface charging during operation, improved stability, and a higher field‐effect mobility. The average field‐effect mobility μFE is found to be 0.27 and 0.41 cm2/V s for the Si‐ and N‐rich gate nitride TFTs, respectively. A further improvement in mobility, μFE =0.61 cm2/V s, is achieved by increasing the N‐rich gate nitride deposition temperature from 250 to 450 °C. These results suggest that N‐rich a‐SiNx:H, deposited at elevated temperatures, yields a more abrupt or ‘‘cleaner’’ a‐SiNx:H/a‐Si:H interface. We also show, for the first time, that using n+ μc‐Si:H source‐drain contacts in place of n+ a‐Si:H improve...

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

Temperature Dependent Characteristics of Hydrogenated Amorphous Silicon thin film Transistors

The characteristics of inverted staggered hydrogenated amorphous silicon/silicon nitride (a-Si:H/a-SiN x :H) thin film transistors (TFTs) are reported between 80 K and 420 K. The TFTs are found to have three distinct transport regimes. Between 80 K to approximately 260 K, the transport in the TFT channel is dominated by electrons hopping between localized gap states of a-Si:H and is analyzed using Motts theory of variable- range hopping. As the tem-perature is increased above ∼260 K the current becomes thermally activated with an activation energy which depends on the gate voltage. The effective field effect mobility, as determined from the TFT characteristics in saturation, is activated in this regime, with an activation energy 0.10 to 0.15 eV. The various activation energies are found to be sensitive to annealing which can be explained by a reduction in deep and shallow states in the a-Si:H active layer. When operated above ∼360 K the TFTs become unstable due to rapid changes in threshold voltage under the applied gate field. The behavior of the threshold voltage is described over the entire temperature range and possible mechanisms are discussed.

Silicon containing polymer in applications for 193 nm high NA lithography processes

The ability to extend 193 nm lithography resolution depends on increasing the numerical aperture (NA) of the exposure system, resulting in smaller depth of focus, which subsequently requires use of thinner photoresists. Bottom antireflective coatings (BARCs) are a necessity, but the organic composition of current 193 nm BARCs offers poor etch selectivity to the photoresist. As a result, image transfer with thin resists is becoming increasingly difficult. It is also more challenging to control reflectivity at high numerical apertures with a thin, single layer BARC. To address these issues, IBM has developed a new class of silicon containing BARCs. These materials exhibit high etch selectivity that will significantly improve the performance of high NA 193 nm lithography. The incorporation of silicon in the backbone of the polymers comprising these BARCS affords a high etch selectivity to conventional organic resists and therefore these polymers can be used as thick planarizing BARCs. The optical constants of these BARCs have been tuned to provide good reflectivity control at NA > 1.2 These materials can also be used as part of a dual layer BARC scheme composed of the thin organosilicon based BARC coated over a planarizing organic underlayer. This scheme has also been optically tuned to provide reflectivity suppression at high incident angles. By utilizing a thick BARC, a novel contact hole shrink process is enabled that allows tapering of the sidewall angle and controlling the post-etch critical dimension (CD) bias. Structures of the silicon containing polymer, formulation chemistry, optical tunability, lithography at high NA and RIE pattern transfer are reported.

Thermal stability and electrical properties of hydrogenated amorphous carbon film

The thermal stability of a plasma‐deposited amorphous carbon film was enhanced by using acetylene heavily diluted with He. The film preserved its hardness even after annealing at ≂590  °C in Ar/H2, while a film deposited in similar conditions in an acetylene/Ar mixture softened significantly. The I‐V characteristics of n‐ and p‐type Si/amorphous carbon heterojunctions showed a 0.2 eV discrepancy. This is attributed to an offset in the conduction band of the amorphous carbon with respect to Si.

Low Au content thermally stable NiGe(Au)W ohmic contacts to n-type GaAs

Thermally stable low‐resistance ohmic contacts to n‐type GaAs incorporating a very thin layer of Au in conjunction with a layered Ni/Ge/W structure are reported. A minimum contact resistance of 0.16 Ω mm was obtained for contacts annealed at ∼650 °C. The contact resistance was ∼0.3 Ω mn after thermal stressing at 400 °C for 20 h. Cross‐sectional transmission electron microscopy reveals a uniformly reacted layer only ∼34 nm deep, making these contacts significantly shallower and more homogeneous than eutectic‐based AuGeNi contacts. X‐ray diffraction shows the presence of NiGe, β‐AuGa, and W phases in the reacted contacts. The volume fraction of the low melting point β‐AuGa phase is considerably reduced from that reported for eutectic‐based AuGeNi contacts. This, along with the presence of the high melting point NiGe compound, explains in part the improved thermal stability and morphology of the low Au content ohmic contacts.

Thermally stable, low‐resistance NiInWNx ohmic contacts to n‐type GaAs prepared by sputter deposition

A new thermally stable, low‐resistance In‐based ohmic contact to n‐type GaAs has been developed. The contacts consist of ion‐beam sputtered Ni (5 nm)/In (5 nm)/Ni (5 nm) layers with a magnetron sputtered WNx overlayer. A low‐contact resistance of ∼0.3 Ω mm was obtained by rapid thermal annealing at 750 °C for ∼5 s. The contact resistance and the excellent contact morphology remained unchanged after annealing at 400 °C for more than 100 h. The present deposition technique provides several advantages over previously reported electron‐beam evaporated In‐based contacts. In particular, the ability to deposit a thick WNx overlayer simplifies GaAs integrated circuit (IC) fabrication by (a) eliminating the need for separate diffusion barrier deposition and patterning steps, and (b) providing for low‐sheet resistance (∼2 Ω/⧠) IC interconnect capabilities. In addition, sputter deposition allows for the controlled incorporation of n‐type dopants into the metallization if further reduction of the contact resistance i...

Post Copper CMP Hybrid Clean Process for Advanced BEOL Technology

A “hybrid” post Cu CMP cleaning process that combines acidic and basic clean in sequence is developed and implemented. The new process demonstrates the strengths of both acidic and basic cleans and achieves a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. It also eliminates the circular ring defects that occur intermittently during roller brush cleans. TXRF scans confirm the reduction of AlOx defects when using the hybrid clean process. XPS spectra show similar Cu surface oxidation states between the basic and hybrid clean processes. As revealed by XRD analysis, surface Cu oxide is dissolved into aqueous solution by the acidic clean chemical. The formation mechanism of circular ring defects and the key to their elimination is discussed.

Oxygen assisted ohmic contact formation mechanism to n‐type GaAs

The presence of oxygen in the top W layer of NiGe(Au)W ohmic contacts to n‐type GaAs is found to play a critical role in reducing their contact resistance. Contacts with sputtered W containing less than 1 at. % oxygen and formed by rapid thermal annealing (RTA) yield a contact resistance (RC) greater than 0.45 Ω mm. Contacts with a reactively sputtered or electron‐beam evaporated metallic W oxide top layer, containing ∼25 at. % oxygen, yield RC’s of less than 0.15 Ω mm. Auger depth profiles of the reacted contacts show a significant outdiffusion of Ga from the GaAs substrate in the presence of the oxygenated W but not in the oxygen‐free contacts. A contact formation mechanism based on the gettering of Ga atoms by oxygen is proposed.The presence of oxygen in the top W layer of NiGe(Au)W ohmic contacts to n‐type GaAs is found to play a critical role in reducing their contact resistance. Contacts with sputtered W containing less than 1 at. % oxygen and formed by rapid thermal annealing (RTA) yield a contact resistance (RC) greater than 0.45 Ω mm. Contacts with a reactively sputtered or electron‐beam evaporated metallic W oxide top layer, containing ∼25 at. % oxygen, yield RC’s of less than 0.15 Ω mm. Auger depth profiles of the reacted contacts show a significant outdiffusion of Ga from the GaAs substrate in the presence of the oxygenated W but not in the oxygen‐free contacts. A contact formation mechanism based on the gettering of Ga atoms by oxygen is proposed.