H. Lifka

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

A novel high-density low-cost diode programmable read only memory

A new stand-alone diode programmable read only memory (DPROM) technology for one-time-programmable memories is presented. The technology features small cell size and low mask count. The memory function is based on the formation of a diode-antifuse by gate oxide breakdown. The functionality of DPROM circuits is demonstrated and the program, read and reliability characteristics are discussed.

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

Hot-carrier degradation is mainly caused by negative oxide-charge generation in the present-day PMOSFETs. We present experimental evidence showing that two more degradation mechanisms are important in the case of deep-submicron PMOSFETs. Firstly, the generation of interface states is significant in the case of sub-half-micron PMOSFETs. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established unambiguously for the first time in PMOSFETs. We measured the bias dependence, the length dependence, and the time dependence separately for all three microscopic degradation mechanisms. We calculated the influence of these three mechanisms on the transconductance degradation. Summation of the three effects yields an excellent description of the experimentally determined time dependence of PMOSFET degradation for many bias conditions and various transistor geometries with either nitrided or conventional gate oxide. >

Two-dimensional transient enhanced diffusion and its impact on bipolar transistors

The impact of transient-enhanced diffusion (TED) and oxidation-enhanced diffusion (OED) on the device performance of advanced Si devices has long been recognized. The short-channel behaviour of MOSFETs is for instance known to be affected. Experimental studies of TED have almost exclusively been restricted to one-dimensional cases, but a full two-dimensional analysis of TED is mandatory to evaluate its impact on device performance. In this paper we present a detailed experimental study of 2D TED for low-dose and high-dose implantations. Furthermore, for the first time the impact of 2D TED due to the external base implantations on the electrical behaviour of single-poly bipolar transistors in a BiCMOS process has been analyzed.<<ETX>>

Positive oxide-charge generation during 0.25 /spl mu/m PMOSFET hot-carrier degradation

A new hot-carrier degradation mechanism becomes important in 0.25 /spl mu/m PMOSFETs. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge.<<ETX>>

New technique for measuring two‐dimensional oxidation‐enhanced diffusion in silicon at low temperatures

In this letter, a new high‐resolution technique is presented for determining the lateral extent of oxidation‐enhanced diffusion (OED). A periodic grid of lines and spacings is used as an oxidation mask. It will be shown that a simple secondary ion mass spectroscopy measurement permits the extraction of parameters in the lateral direction with a resolution which can be as good as 10 nm. The lateral extent of OED is depth dependent, consistent with a physical model of point‐defect recombination at the Si/SiO2 interface.

N/sub 2/O nitrided gate dielectric technology for 0.25 mu m CMOS

A technology for thin N/sub 2/O nitrided gate oxide was developed for 0.25 mu m CMOS. A gate dielectric of 7.5 nm thickness was grown using a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900 degrees C, the second step is nitridation in pure N/sub 2/O at 950 degrees C. The use of lightly nitrided gate dielectrics improved the gate oxide quality and did not degrade the MOS device properties. Furthermore, boron diffusion through the thin dielectric of BF/sub 2/ doped poly gates was suppressed by N/sub 2/O nitridation.<<ETX>>

Lightly nitrided gate oxides for 0.25 mm CMOS

Abstract A N 2 O lightly nitrided gate dielectric technology is developed for 0.25 μm CMOS. Gate dielectric with a thickness of 7.5 nm is grown in a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900° C , the second step is nitridation in pure N 2 O at 950° C . The use of lightly nitrided gate dielectrics improves the gate oxide quality and has no adverse effects on devices. Furthermore boron diffusion through thin gate oxide of BF + 2 doped poly gates is suppressed. This makes it possible to use low energy BF + 2 implants for shallow drain formation. The physical and electrical characterisation of MOS capacitors and 0.25 μm transistors will be presented.

New hot-carrier degradation mechanisms in 0.25 /spl mu/m PMOSFETs

PMOSFET hot-carrier reliability is often proposed to he limited by negative oxide charge. We show that interface states determine the lifetime in deep submicron PMOSFETs. Clear evidence for additional positive oxide-charge generation is presented for the first time. The bias-length and time dependences are measured for all three degradation mechanisms. Combining these three mechanism describes the time dependence of PMOSFET degradation convincingly for many geometries at many bias conditions.<<ETX>>

Effects of high normal electric fields in deep submicron MOSFET's

The implications of high normal electric fields in MOSFETs on device simulations are discussed. Comparison of simulations with data of experimental MOS devices shows that, even at room temperature, the electric fields generated by high levels of channel doping affect the threshold voltage by quantum-mechanical effects. Furthermore, the surface mobility is reduced by high normal fields, but can still be modeled accurately when calculated as a function of the effective electric field.