M.J. van Dort

A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions

Abstract The transistor parameters of state-of-the-art MOSFETs are affected by quantisation effects of the carrier motion in the inversion channel. To account for these effects in classical device stimulators, we show that a better modeling of the silicon bandgap at inversion conditions is ifE g QM = E g CONV + 13 9 Δϵ in which Δϵ is the position of the first energy level with respect to the bottom of the conduction band. The improved modeling of the bandgap leads to a new model for the intrinsic carrier concentration ni. The model for ni has been tested against measurements and against self-consistent QM calculations. Excellent agreement is obtained.

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

Non-local impact ionization in silicon devices

In small bipolar and MOS transistors, the electrons gain much less energy than according to the maximum electric field. This is due to nonlocal electron heating and the small width of the E-field peak. The simplified energy balance equation with the energy relaxation length lambda /sub e/ as parameter gives the electron temperature for a given electric field distribution. From a series of MBE (molecular beam epitaxy)-grown bipolar transistors and scaled submicron MOS transistors, lambda /sub e/=650 AA was found. With the calculated temperature distribution and known empirical models for the impact ionization, avalanche (substrate) currents are accurately predicted. This procedure can easily be implemented, as postprocessing, in existing device simulators with hardly any extra computation time. It extends in a consistent way the validity range of these simulators to future device generations.<<ETX>>

Quantum-mechanical threshold voltage shifts of MOSFETs caused by high levels of channel doping

The impact of high doping levels on the threshold voltage of MOS transistors is discussed. The threshold voltage of surface channel devices is shown to be affected through the quantum-mechanical splitting of the energy levels in the conduction band. A significant threshold voltage shift is reported at room temperature for deep-submicron n-channel devices and needs to be taken into account in the design of the devices. A simple analytical model to account for this effect is proposed.<<ETX>>

Circuit sensitivity analysis in terms of process parameters

A new methodology for sensitivity analysis at circuit level in terms of process parameters is presented. Response functions for long-channel MOSFETs are found from process and device simulations. Responses for a device with arbitrary dimensions are subsequently calculated using the MOS MODEL 9 scaling rules.

Two-dimensional transient enhanced diffusion and its impact on bipolar transistors

The impact of transient-enhanced diffusion (TED) and oxidation-enhanced diffusion (OED) on the device performance of advanced Si devices has long been recognized. The short-channel behaviour of MOSFETs is for instance known to be affected. Experimental studies of TED have almost exclusively been restricted to one-dimensional cases, but a full two-dimensional analysis of TED is mandatory to evaluate its impact on device performance. In this paper we present a detailed experimental study of 2D TED for low-dose and high-dose implantations. Furthermore, for the first time the impact of 2D TED due to the external base implantations on the electrical behaviour of single-poly bipolar transistors in a BiCMOS process has been analyzed.<<ETX>>

New technique for measuring two‐dimensional oxidation‐enhanced diffusion in silicon at low temperatures

In this letter, a new high‐resolution technique is presented for determining the lateral extent of oxidation‐enhanced diffusion (OED). A periodic grid of lines and spacings is used as an oxidation mask. It will be shown that a simple secondary ion mass spectroscopy measurement permits the extraction of parameters in the lateral direction with a resolution which can be as good as 10 nm. The lateral extent of OED is depth dependent, consistent with a physical model of point‐defect recombination at the Si/SiO2 interface.

The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors

An experimental study of hot carrier degradation and power supply voltage scaling of deep-submicron NMOS devices is presented. Devices were optimized for processes with design rule between 2 mu m and 0.17 mu m. Charge pumping measurements showed that the lifetime based on interface state generation in the devices was determined only by I/sub sub//I/sub d/ and the drain current. It did not depend on gate length, oxide thickness, and substrate doping. The lifetime (determined by shifts in the maximum linear transconductance) of the devices with minimum gate length of different processes fall on a single life in plots of tau *I/sub d/ versus I/sub sub//I/sub d/. This behavior can be explained by the impact of interface damage on the transistor parameters of these devices. Light emission spectra and device simulation showed that nonlocal carrier heating becomes important for devices from deep-submicron processes. As a result the power supply voltage is almost independent of design rule for the deep-submicron process (V/sub dd/<or=2.5 V).<<ETX>>

Effects of high normal electric fields in deep submicron MOSFET's

The implications of high normal electric fields in MOSFETs on device simulations are discussed. Comparison of simulations with data of experimental MOS devices shows that, even at room temperature, the electric fields generated by high levels of channel doping affect the threshold voltage by quantum-mechanical effects. Furthermore, the surface mobility is reduced by high normal fields, but can still be modeled accurately when calculated as a function of the effective electric field.

Sensitivity Analysis of an Industrial CMOS Process using RSM Techniques

This paper describes a method to identify the process parameters responsible for the spread in the transistor parameters. The method consists of modeling the response surfaces for the transistor parameters and the correlations between them in terms of process variables. Incorporation of the correlations in the analysis turned out to be essential in order to correctly identify the cause for the fluctuations in the transistor parameters.