Andy Eu-Jin Lim

Review of Silicon Photonics Foundry Efforts

Silicon photonics have progressed to a point where the next step for commercialization depends on the accessibility of manufacturing foundries. The implementation of a fabless foundry model using standardized process technology platforms is crucial for that to occur. Research and development (R&D) foundries are beginning to play bigger roles in transforming silicon photonics into a mature technology for mass production. R&D foundry services such as multi-project wafer (MPW) shuttles, customized process developmental runs and small volume manufacturing are discussed. The development of commercial foundries for low cost, high volume production is also shown to be underway, and key results from an on-going effort to set-up a manufacturing silicon photonics foundry line are presented.

Ultralow drive voltage silicon traveling-wave modulator

There has been great interest in the silicon platform as a material system for integrated photonics. A key challenge is the development of a low-power, low drive voltage, broadband modulator. Drive voltages at or below 1 Vpp are desirable for compatibility with CMOS processes. Here we demonstrate a CMOS-compatible broadband traveling-wave modulator based on a reverse-biased pn junction. We demonstrate operation with a drive voltage of 0.63 Vpp at 20 Gb/s, a significant improvement in the state of the art, with an RF energy consumption of only 200 fJ/bit.

Low power 50 Gb/s silicon traveling wave Mach-Zehnder modulator near 1300 nm

A silicon traveling-wave Mach-Zehnder modulator near 1300 nm is demonstrated to operate at 50 Gb/s with a differential 2 Vpp signal at 0 V reverse bias, achieving a 800 fJ/bit power consumption.

Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height (PhiB N) of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in PhiB N is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.

Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect

We demonstrate compact, broadband, ultralow loss silicon waveguide crossings operating at 1550 nm and 1310 nm. Cross-wafer measurement of 30 dies shows transmission insertion loss of - 0.028 ± 0.009 dB for the 1550 nm device and - 0.017 ± 0.005 dB for the 1310 nm device. Both crossings show crosstalk lower than - 37 dB. The devices were fabricated in a CMOS-compatible process using 248 nm optical lithography with a single etch step.

Wide

For the first time, we demonstrate experimentally that by using HfLaO high-kappa gate dielectric, the flat-band voltage (Vfb) and the threshold voltage (Vth) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-degC annealing required by a conventional CMOS source/drain activation process. As prototype examples shown in this letter, TaN gate with effective work function Phim,eff~3.9-4.2 eV and Pt gate with Phim,eff~5.5 eV are reported. A specific model based on the interfacial dipole between the metal gate and the HfLaO is proposed to interpret the results. This provides an additionally practical guideline for choosing the appropriate gate stacks and dielectric to meet the requirements of future CMOS devices

V_{\rm fb}

Germanium-on-silicon photodetectors have been heavily investigated in recent years as a key component of CMOS-compatible integrated photonics platforms. It has previously been shown that detector bandwidths could theoretically be greatly increased with the incorporation of a carefully chosen inductor and capacitor in the photodetector circuit. Here, we show the experimental results of such a circuit that doubles the detector 3dB bandwidth to 60 GHz. These results suggest that gain peaking is a generally applicable tool for increasing detector bandwidth in practical photonics systems without requiring the difficult process of lowering detector capacitance.

and

Large-scale optical systems in silicon can become a reality by building upon the existing infrastructure. Due to the shifting economics of silicon photonics, some cost-effective fabless silicon products may even emerge over the next several years.

V_{\rm th}

We report a novel evanescent-coupled germanium (Ge) electro-absorption (EA) modulator with a small active area of 16 μm2 giving an extinction ratio of at least 10 dB for a wavelength range of 1580-1610 nm. The modulation efficiency of the modulator at this wavelength range was
~2 dB/V. In addition, monolithic integration of both evanescent-coupled Ge EA modulator and Ge p-i-n photodetector is demonstrated for the first time.

Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics

We have developed a novel epitaxial nickel-aluminide silicide (NiSi_2-xAl_x) to reduce the Schottky-barrier height (SBH) and series resistance in n-channel MuGFETs with dopant-segregated Schottky-Barrier source/drain (DSS). 10% substitutional incorporation of Al in the Si matrix at the silicide-Si interface leads to a 37% reduction in the intrinsic SBH of nickel silicide. A further 42% effective reduction in the DSS SBH was attained with the combination of NiSi_2-xAl_x and DSS technology. Saturation drive current enhancement of 94% for NiSi_2-xAl_x DSS MuGFETs over NiSi DSS MuGFETs was achieved, attributed to SBH lowering, series resistance reduction and possibly silicide strain effects. As a result, an excellent drive current of 882 muA/mum at V_GS-V_T =V_DS = 1.2 V was achieved for NiSi_2-xAl_xDSS MuGFETs with 55 nm gate length.