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Dive into the research topics where Rinus T. P. Lee is active.

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Featured researches published by Rinus T. P. Lee.


IEEE Electron Device Letters | 2009

Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

Rinus T. P. Lee; Andy Eu-Jin Lim; K. L. Tan; Tsung-Yang Liow; D. Z. Chi; Yee-Chia Yeo

In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height (PhiB N) of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in PhiB N is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.


symposium on vlsi technology | 2006

Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement

Tsung-Yang Liow; K. L. Tan; Rinus T. P. Lee; Anyan Du; Chih-Hang Tung; Ganesh S. Samudra; Won-Jong Yoo; N. Balasubramanian; Yee-Chia Yeo

We report the demonstration of 25 nm gate length L<sub>G</sub> tri-gate FinFETs with Si<sub>0.99</sub>C<sub>0.01</sub> source and drain (S/D) regions. The strain-induced mobility enhancement due to the Si<sub>0.99</sub>C<sub>0.01</sub> S/D leads to a drive current I<sub>Dsat</sub> improvement of 20% at a fixed off-state current I<sub>off</sub> of 1times10<sup>-7</sup> A/mum. With additional channel strain engineering, FinFETs incorporating Si<sub>0.99</sub>C<sub>0.01</sub> S/D and a tensile-stress silicon nitride (SiN) capping etch-stop layer (ESL) achieve an I<sub>Dsat</sub> enhancement of 56%


symposium on vlsi technology | 2007

Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs

Rinus T. P. Lee; Tsung-Yang Liow; K. L. Tan; Andy Eu-Jin Lim; Chee-Seng Ho; Keat-Mum Hoe; M. Y. Lai; T. Osipowicz; Guo-Qiang Lo; Ganesh S. Samudra; D. Z. Chi; Yee-Chia Yeo

We have developed a novel epitaxial nickel-aluminide silicide (NiSi<sub>2-x</sub>Al<sub>x</sub>) to reduce the Schottky-barrier height (SBH) and series resistance in n-channel MuGFETs with dopant-segregated Schottky-Barrier source/drain (DSS). 10% substitutional incorporation of Al in the Si matrix at the silicide-Si interface leads to a 37% reduction in the intrinsic SBH of nickel silicide. A further 42% effective reduction in the DSS SBH was attained with the combination of NiSi<sub>2-x</sub>Al<sub>x</sub> and DSS technology. Saturation drive current enhancement of 94% for NiSi<sub>2-x</sub>Al<sub>x</sub> DSS MuGFETs over NiSi DSS MuGFETs was achieved, attributed to SBH lowering, series resistance reduction and possibly silicide strain effects. As a result, an excellent drive current of 882 muA/mum at V<sub>GS</sub>-V<sub>T</sub> =V<sub>DS</sub> = 1.2 V was achieved for NiSi<sub>2-x</sub>Al<sub>x</sub>DSS MuGFETs with 55 nm gate length.


IEEE Electron Device Letters | 2008

Nickel-Silicide:Carbon Contact Technology for N-Channel MOSFETs With Silicon–Carbon Source/Drain

Rinus T. P. Lee; Li-Tao Yang; Tsung-Yang Liow; K. L. Tan; Andy Eu-Jin Lim; Kah-Wee Ang; Doreen M. Y. Lai; Keat Mun Hoe; Guo-Qiang Lo; Ganesh S. Samudra; D. Z. Chi; Yee-Chia Yeo

To explore the potential of nickel-silicide:carbon (NiSi:C) as contact technology for MOSFETs with silicon-carbon (Si:C) source/drain (S/D) regions, we examined the effects of incorporating 1.0 at.% of carbon in Si prior to nickel silicidation. The addition of carbon was found to improve the morphological and phase stability of NiSi:C contacts. This is possibly due to the presence of carbon at the NiSi:C grain boundaries and NiSi:C/Si interface, which will modify the grain-boundary and interfacial energies. This will influence the kinetics of NiSi:C silicidation. In this letter, we have also demonstrated the first integration of NiSi:C contacts in MOSFETs with Si:C S/D regions. We further show that NiSi:C silicidation suppresses the formation of active deep-level defects, leading to superior n+/p junction characteristics.


IEEE Electron Device Letters | 2007

N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide

Rinus T. P. Lee; Andy Eu-Jin Lim; K. L. Tan; Tsung-Yang Liow; Guo-Qiang Lo; Ganesh S. Samudra; D. Z. Chi; Yee-Chia Yeo

We have fabricated n-channel 25-nm gate length FinFETs with Schottky-barrier source and drain featuring a self-aligned ytterbium silicide (YbSi<sub>1.8</sub>). A low-temperature silicidation process was developed for the formation of the low electron barrier height YbSi <sub>1.8</sub> phase, without reaction with SiO<sub>2</sub> isolation or SiN spacer materials, enabling integration in a CMOS fabrication process flow. The fabricated device exhibits good device characteristics with a drive current of 241 muA/mum at V<sub>DS</sub>=V<sub>GS</sub>-V<sub>t</sub>=1 V, I<sub>on</sub>/I<sub>off</sub>=10<sup>4</sup> at V<sub>DS</sub>=1.1 V, subthreshold swing of 125 mV/decade, and drain-induced barrier lowering of 0.26 V/V


IEEE Transactions on Electron Devices | 2008

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon

Tsung-Yang Liow; K. L. Tan; Doran Weeks; Rinus T. P. Lee; Ming Zhu; Keat-Mun Hoe; Chih-Hang Tung; Matthias Bauer; Jennifer Spear; S.G. Thomas; Ganesh S. Samudra; N. Balasubramanian; Yee-Chia Yeo

Phosphorus in situ doped (Si1-yCy) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source and drain regions of double-gate -oriented (110)-sidewall FinFETs to induce tensile strain in the silicon channel. In situ doping removes the need for a high-temperature spike anneal for source/drain (S/D) dopant activation and thus preserves the carbon substitutionality in the SiC:P films as grown. A strain-induced enhancement of 15% and 22% was obtained for n-channel FinFETs with 1.7% and 2.1% carbon incorporated in the S/D, respectively.


IEEE Electron Device Letters | 2007

(\hbox{Si}_{1 - y}\hbox{C}_{y})

K. L. Tan; Tsung-Yang Liow; Rinus T. P. Lee; Keat Mun Hoe; Chih-Hang Tung; N. Balasubramanian; Ganesh S. Samudra; Yee-Chia Yeo

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.


Journal of Applied Physics | 2005

Source and Drain Stressors With High Carbon Content

D. Z. Chi; Rinus T. P. Lee; S. J. Chua; Sungjoo Lee; S. Ashok; D. L. Kwong

Current–voltage-temperature characterization has been performed on NiGe∕n-(100)Ge Schottky contacts that were formed by the solid-state reaction of Ni with Ge. An effective barrier height of 0.732–0.735eV, which is larger than the band-gap 0.66eV of Ge, was obtained. A physical model describing the current transport mechanism in a Schottky contact with a barrier height larger than the semiconductor band gap is proposed and discussed on the basis of thermionic-field emission as the dominant transport mechanism. The observation of a barrier height larger than the semiconductor band gap should be of technological importance as it suggests that NiGe is an ideal contact and Schottky source/drain material in Ge-based p-metal-oxide-semiconductor field-effect-transistors.


IEEE Electron Device Letters | 2008

Strained p-Channel FinFETs With Extended

K. L. Tan; Ming Zhu; Wei-Wei Fang; Mingchu Yang; Tsung-Yang Liow; Rinus T. P. Lee; Keat Mun Hoe; Chih-Hang Tung; N. Balasubramanian; Ganesh S. Samudra; Yee-Chia Yeo

We report the integration of a new liner stressor comprising diamond-like carbon (DLC) film over a p-channel transistor. A high compressive stress of 6.5 GPa was achieved in a high-stress film with a thickness of 27 nm. A 74% enhancement in drive current was observed for the strained device with DLC liner as compared to a control device without DLC liner. Due to its much higher intrinsic stress value compared to conventional SiN films, a thinner DLC layer can induce comparable amount of stress in the transistor channel compared to a thicker SiN. The DLC material is a potential next-generation high-stress and low-permittivity liner stressor material suitable for application in transistors with aggressively scaled pitch dimensions.


IEEE Electron Device Letters | 2007

\Pi

Tsung-Yang Liow; K. L. Tan; Rinus T. P. Lee; Chih-Hang Tung; Ganesh S. Samudra; N. Balasubramanian; Yee-Chia Yeo

The performance of n-channel (110)-sidewall trigate fin-shaped field-effect transistors (FinFETs) is seriously compromised as (110) surfaces have significantly lower electron mobility than (100) surfaces. Straining the channel in (110)-sidewall FinFETs using lattice-mismatched silicon-carbon (Si1-yCy) stressors alone was experimentally determined to be far less effective than doing the same with (100)-sidewall FinFETs. By additionally incorporating a tensile silicon nitride contact etch-stop layer, the increase in longitudinal tensile stress and the introduction of vertical compressive stress result in significant further IDsat enhancement, highlighting the importance of the vertical compressive stress component for enhancing (110)-sidewall FinFET performance.

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Yee-Chia Yeo

National University of Singapore

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Ganesh S. Samudra

National University of Singapore

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K. L. Tan

National University of Singapore

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N. Balasubramanian

National University of Singapore

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Chih-Hang Tung

National University of Singapore

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Ming Zhu

National University of Singapore

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