Fumihiro Inoue

Investigation of Advanced Dicing Technologies for Ultra Low-k and 3D Integration

The introduction and use of ultra low-k dielectric materials in an attempt to achieve better die performance brought new challenges to the wafer singulation / dicing process. Ultra low-k dielectric materials can easily get damaged during conventional blade dicing due to their brittleness. Thus, there is a need to investigate alternative or more advanced dicing techniques that can deliver successful dicing processes without inducing stress or damage. Apart from looking at the compatibility of the different dicing techniques with (ultra) low-k dielectric materials, the integration of these different dicing techniques into the different 3D-technology configurations was also investigated. This paper reports on the post dicing results and the challenges for 3D technology for the following different dicing technologies: blade dicing, laser grooving + blade dicing, laser grooving + plasma dicing, stealth dicing, plasma dicing, and laser full cut dicing.

3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects

In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.

Development of multi-stack dielectric wafer bonding

We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.

Die to wafer 3D stacking for below 10um pitch microbumps

Processing of bump-less or embedded microbumps is introduced in this paper as an approach which enables scaling microbumps for below 10um pitches. Landing wafer is standard damascene process and in top wafer bumps are embedded in a soft backed polymer. Later during thermo-compression bonding this polymer is cured to bond two chips together. Process flow and results of TC bonding is discussed in this paper.

Highly conformal and adhesive electroless barrier and Cu seed formation using nanoparticle catalyst for realizing a high aspect ratio cu-filled TSV

A conformal diffusion barrier was formed in a high aspect ratio through-silicon via (TSV) using electroless plating. Dense adsorption of Pd nanoparticle catalyst on SiO2 assisted the formation of a thin electroless CoWB layer, on which an electroless Cu seed layer could be deposited. The adhesion strength of the CoWB layer was improved with addition of adequate amount of saccharine and conformal deposition property was obtained with addition of SPS.