Erik Sleeckx

Performance improvement of tall triple gate devices with strained SiN layers

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

Scaling to Sub- 1 nm Equivalent Oxide Thickness with Hafnium Oxide Deposited by Atomic Layer Deposition

The implementation of HfO 2 gate dielectrics in sub-45 nm devices requires optimization of nanometer-thin HfO 2 layers, deposited, e.g., by atomic layer deposition (ALD). In this work, we optimize ALD conditions such as precursor pulse time and deposition temperature for HfO 2 layers with physical thicknesses below 2 nm. Additionally, we investigate intermediate treatments in the ALD reaction cycle, such as exposure to gas-phase moisture or remote plasma at low temperature and thermal anneals. Such intermediate treatments affect both growth-per-cycle (GPC) and Cl-impurity content of the HfO 2 layers. The analysis of the process modifications allows a better understanding of the reaction mechanisms. H 2 O pulse times of 10 s must be applied to achieve saturation in GPC and Cl content. Using saturated H 2 O pulses decreases the gate leakage current in the sub-1 nm equivalent oxide thickness (EOT) range. The GPC is enhanced from ∼1.8 Hf/nm 2 for conventional ALD to 4 Hf/nm 2 for intermediate plasma treatments at low temperature. Intermediate anneals reduce the Cl content by about two orders of magnitude. Sufficient hydroxylation of the HfO 2 surface is one important factor controlling electrical properties in the sub-1 nm EOT range. The reduction of the Cl content does not systematically improve the electrical properties.

Properties of porous HSQ-based films capped by plasma enhanced chemical vapor deposition dielectric layers

This article presents a study on Dow Corning® XLK™, an inorganic porous material with about 50% porosity and a dielectric constant of 2.0. It focuses on matters linked to sealing the porous film by depositing a plasma enhanced chemical vapor deposition (PECVD) dielectric cap layer. The study shows that the material can be modified during cap deposition due to the fast diffusion of reactants and radicals through the porous network, and acquire totally new properties which can be either beneficial or detrimental, depending on the chosen process. In particular, it is found that cap deposition processes on XLK in an oxidizing ambient, as used for SiO2 deposition, should be avoided. On the other hand, a beneficial modification of the dielectric film has been observed after SiC:H capping. It is also shown that there exists a critical thickness of capping material below which the cap layer reveals the presence of pinholes. The critical thickness value for a PECVD SiC:H cap layer on top of an XLK film is around 2...

On the scalability of source/drain current enhancement in thin film sSOI

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques

MOS FET’s and capacitors with a gate oxide containing a Silicon-Rich-Oxide (SRO) layer were fabricated. Memory action occurs through trapping of charge in the SRO-layer. Pulsed Current-Voltage techniques recording Id-Vg and C-V-curves have been used to determine the cell characteristics. Programming and erasing can be achieved by applying ±8V pulses with 100ms pulse width. Faster programming and pulses on the gate electrode. The cells have an endurance of 10 5 cycles and an estimated retention of 10 years.

Characterisation and integration feasibility of JSR's low-k dielectric LKD-5109

Increasing the circuit density is driving the need for lower permittivity interlayer dielectrics (ILD) to reduce the capacitance between long parallel lines. JSRs LKD-5109, an MSQ-based material, is one of such low-k materials for the 65-nm node. The feasibility of integrating LKD-5109 in a single inlaid structure has been investigated. Thermal stability, chemical compatibility to stripping agents and CMP slurries are verified. A single damascene structure incorporating a dual CVD hard mask has been attempted and electrical results have been evaluated.

Process Optimization and Integration of Trimethylsilane-Deposited α-SiC:H and α-SiCO:H Dielectric Thin Films for Damascene Processing

The semiconductor grade organosilicon gas trimethylsilane (Dow Corning Z3MS) can be used to deposit unique amorphous hydrogenated silicon carbide (α-SiC:H)-based alloy films that exhibit desirable properties such as chemical resistance, low stress. low permittivity, and low leakage. These film characteristics are ideal for applications in Cu-damascene interconnect technology. In this work, the results of a comprehensive study of Z3MS plasma enhanced chemical vapor deposition (PECVD) dielectric films are reported where all depositions were performed in commercial production PECVD equipment. Processing for α-SiC:H films deposited from Z3MS/He mixtures was optimized for deposition rate, uniformity, and permittivity. The processing parameters can be tuned for relative permittivity down to κ ∼ 4.2 making α-SiC:H an attractive substitute for PECVD silicon oxide or silicon nitride. Using mixtures of Z3MS and N 2 O precursors, α-SiCO:H films were deposited with very high deposition rates and film permittivity as low as κ ∼ 2.5. These films have been applied in damascene technology. Physical properties and stability of blanket films were studied. Measurement of relative permittivity, leakage current, and breakdown voltage was performed on metal/dielectric/metal structures. Fourier transform infrared, X-ray photoelectron, and high-energy ion scattering spectrometry were used to determine bonding and film compositions. Integration issues related to deep ultraviolet lithography, dry etch, strip, and metallization are discussed. Optimized film processes were integrated into 0.18 μm Cu damascene interconnect process technology and the electrical results were compared to standard PECVD oxide. The results of these studies indicate that the device performance improvements inferred from the blanket film properties can be realized in fully integrated interconnect structures.

Optimization of low temperature silicon nitride processes for improvement of device performance

This paper gives some insights in the applications where PECVD nitrides can be introduced to replace the LPCVD layers and how the process parameters need to be varied to obtain the desired properties. Film properties like stress, hydrogen content, wet etch rate and deposition rate are reported. The nitrides are optimized for specific applications and examples on the influence of nitride properties on device performance are given. It is important to investigate that the advantage of the high film integrity of nitride layers used in the past is not lost due to the strong demand for developing new process schemes with low thermal budget layers. We show that PECVD films are a valid alternative for LPCVD and that the majority of the film properties satisfy the criteria to use PECVD films as contact-etch-stop layers, silicidation blocking films and spacer materials.

Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.

Review of flash design rules for closed-die forgings

Abstract In an extensive literature review the authors have found 16 different rules or procedures for calculating the flash gap dimensions T (thickness of flash), W (width of flash land) and ratio W/T . These rules were implemented in an application program in an interactive CAD environment. For 10 existing axi-symmetrical industrial forgings, the flash dimensions were calculated with these rules and compared with the flash dimensions actually used to produce these forgings in industry.