John Slabbekoorn

Cost components for 3D system integration

The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack testing is evaluated when considering the system integration cost for each one of the 3D stacking methods. In addition the size of the stacked active dies is parameterized and the effect on the system integration cost is explored. Also, the impact of pre-stack testing on interposer in relation to processing yield and the size of the stacked active dies is investigated.

Room temperature and zero pressure high quality oxide direct bonding for 3D self-aligned assembly

To keep up with the pace of decreasing transistor channel length, the demand for smaller pitch size is pushing 3D IC research into new approaches for stacking. As the pitch size decreases, the thickness of interconnection also decreases. During stacking, a small misalignment may lead to poor interconnection or even connection failure. This has led 3D IC research to pursue higher alignment accuracy during stacking. One such stacking approach that is being considered is 3D self-alignment. To facilitate highly accurate alignment it is also important to have good quality immediate bonding that can further reduce chances of misalignment during handling. In this work, we demonstrate a very high quality bonding between two similar dies with oxide capping layer, as well as different cleaning approach and the bonding test.

Large area interposer lithography

Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfield exposures. Overlay metrology structures are used to confirm the relative placement of the subfields to construct the interposer. Routing lines from 1.5 to 4.0 μm in width are evaluated to measure critical dimension (CD) control where the lines cross the subfield boundaries. CD metrology at the bottom and top of the photoresist is performed using a top down CD-SEM. Finally large area test interposers are patterned using two subfields on a 1X stepper and processed through a Cu electroplating module for detailed characterization. The CD control of routing lines as they cross the subfield boundary can be optimized by using a shaped or tapered line end design. Lithography simulation using Prolith modeling software by KLA-Tencor is matched to experimental results and then used to evaluate performance of various line end designs. Larger latitude for overlap error was observed for the tapered line end compared to the standard square line end. The experimental and modeled results in this study show the capability of using stepper lithography to produce large area interposers with 1.5 μm I/O routing line dimensions.

Investigation of Co Thin Film as Buffer Layer Applied to Cu/Sn Eutectic Bonding and UBM With Sn, SnCu, and SAC Solders Joints

The demand of small-feature-size, high-performance, and dense I/O density applications promotes the development of fine-pitch vertical interconnects for 3-D integration where microbumps are fabricated with Cu through-silicon via and under-bump metallization. Small dimension Cu/Sn bonding has to be developed to address the needs of increasing I/O density and shrinking pitch and size for future applications. For fine-pitch microbumps, it is important to select right UBM and solder materials to obtain lower UBM consumption, which means lower intermetallic compound (IMC) thickness. To find the best binary system material for fine-pitch microbumps with a different annealing temperature and time, we investigate the interfacial reaction and intermetallic compound morphologies of Co UBM with Sn, SnCu, and SAC solders. A thin, uniform, and single-phase IMC between solder and UBM facilitates finer pitch and more reliable microbumps development; the higher activation energies imply longer solder lifetime. Co, as an ultrathin buffer layer (UBL), is also used in Cu/Sn bonding. A comparison between Cu–Sn bonding with and without UBL is conducted. From this study, Co as UBL and UBM is explored and could be applied in semiconductor applications.

Overlay performance of through Si via last lithography for 3D packaging

Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smaller TSV diameters, back-to-front overlay becomes a critical parameter because via landing pads on the first metal level must be large enough to include both the TSV critical dimension (CD) and overlay variations. In this paper we investigate the long term capability of a Dual Side Alignment (DSA) lithography system for printing 5 μm and smaller TSV features. DSA lithography is used to pattern the TSV feature, and Stepper Self Metrology (SSM) is performed to verify the overlay after photoresist development. Multiple stepper lithography fields per wafer and multiple wafers per lot are measured to obtain a statistically significant data set for wafer lot overlay analysis. In addition, multiple wafer lots were processed and measured to establish long term overlay performance and stability. In order to independently verify the SSM overlay data, dedicated electrical structures were designed and placed on a Via Last TSV test chip. These structures allow the TSV diameter and TSV overlay to be measured electrically after lot completion. Vector plots were used to compare the SSM overlay and electrical overlay data.