Fernando Medeiro

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology. >

A statistical optimization-based approach for automated sizing of analog cells

This paper presents a CAD tool for automated sizing of analog cells using statistical optimization in a simulation based approach. A nonlinear penalty-like approach is proposed to define a cost function from the performance specifications. Also, a group of heuristics is proposed to increase the probability of reaching the global minimum as well as to reduce CPU time during the optimization process. The proposed tool sizes complex analog cells starting from scratch, within reasonable CPU times (approximately 1 hour for a fully differential opamp with 51 transistors), requiring no designer interaction, and using accurate transistor models to support the design choices. Tool operation and feasibility is demonstrated via experimental measurements from a working CMOS prototype of a folded-cascode amplifier.

High resolution CMOS current comparators: design and applications to current-mode function generation

This paper uses fundamental models to derive design conditions for maximum speed and resolution in CMOS transimpedance comparators. We distinguish two basic comparator architectures depending on whether the input sensing node is resistive or capacitive, and show that each type yields advantages for different ranges of input current. Then, we introduce a class of current comparator structures which use nonlinear sensing and/or feedback to combine the advantages of capacitive-input and resistive-input architectures. Two members of this class are presented demonstrating resolution levels (measured on silicon prototypes) in the range of pAs. They exhibit complementary functional features: one, the current steering comparator, displays better transient response in the very comparison function, while operation of the other, the current switch comparator, is easily extended to support systematic generation of nonlinear transfer functions in current domain. The paper explores also this latter extension, and presents current-mode circuit blocks for systematic generation of nonlinear functions based on piecewise-linear (PWL) approximation. Proposals made in the paper are demonstrated via CMOS prototypes in two single-poly CMOS n-well technologies: 2μm and 1.6μm. These prototypes show measured input current comparison range of 140 dB, resolution and offset below 10 pA, and operation speed two orders of magnitude better than that of conventional resistive-input circuits. Also, measurements from the PWL prototypes show excellent rectification properties (down to a few pAs) and small linearity errors (down to 0.13%).

Modeling opamp-induced harmonic distortion for switched-capacitor /spl Sigma//spl Delta/ modulator design

This communication reports a new modeling of opamp-induced harmonic distortion in SC /spl Sigma//spl Delta/ modulators, which is aimed at the optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer of charge in a SC integrator and use power expansion and nonlinear fitting to obtain analytical models to represent harmonic distortion as function of the opamp finite gain-bandwidth (GB), slew-rate (SR) and nonlinear DC gain. Calculated models apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. We show that results provided by the new analytical models fit well to that obtained by simulation in time domain and have accuracy levels much larger than that provided by previously reported modeling approaches.<<ETX>>

Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.

A 13-bit, 2.2-MS/s, 55-mW multibit cascade /spl Sigma//spl Delta/ modulator in CMOS 0.7-/spl mu/m single-poly technology

This paper presents a CMOS 0.7-/spl mu/m /spl Sigma//spl Delta/ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1/sub mb/ architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1/sub single-bit/ modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.

High Resolution CMOS Current Comparators

A 2¿m CMOS current comparator prototype is presented with an input current comparison range of 140dB and virtual zero offset(≪10pA). The circuit uses capacitive sensing for high resolution and nonlinear feedback to achieve small input voltage variations in the complete input current range. Operation speed for low current is abot two orders of magnitude larger than for conventional circuits. Simplified modeling issues are used to compare alternative comparator architectures.

CMOS telecom data converters

1: Nyquist-Rate Converters: An Overview.- 2: Sigma-Delta CMOS ADCs: An Overview of the State-of-the-Art.- 3: Current-Steering High-Speed D/A Converters For Communications.- 4: Cmos Comparators.- 5: Folding/Interpolating ADCs Analog Preprocessing Techniques For High-Speed 8-Bit ADC.- 6: High-Speed Flash ADCs - Design Issues Of A 6 Bit, 1 GHz CMOS Flash ADC.- 7: Logarithmic Analogue-To-Digital Converters.- 8: Single-Loop Multi-Bit Sigma-Delta Modulators.- 9: High-Order Cascade Multi-Bit ?? Modulators.- 10: Continuous-Time Sigma-Delta For IF.- 11: Bandpass Sigma-Delta A/D Converters: Fundamentals, Architectures And Circuits.- 12: Decimation Filter Design For Sigma-Delta Converters.- 13: Line Drivers: Efficiency, Linearity, Bandwidth.- 14: PGAs and Filters.- 15: Design Methodologies for Sigma-Delta Converters.- 16: Systematic Computer - Aided Design Methodology for CMOS Data Converters.

Fourth-order cascade SC /spl Sigma//spl Delta/ modulators: a comparative study

Fourth-order cascade /spl Sigma//spl Delta/ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires careful consideration of their performance degradations due to the hardware nonidealities. This paper presents a comparative study of the influence of finite op-amp gain and capacitor mismatch on the performance of fourth-order cascade /spl Sigma//spl Delta/ modulators realized by means of switched-capacitor circuits. It considers single-bit and multibit quantizers and draws a number of comparative remarks validated by time-domain behavioral simulations.Fourth-order cascade modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires careful consideration of their performance degradations due to the hardware nonidealities. This paper presents a comparative study of the influence of finite op-amp gain and capacitor mismatch on the performance of fourth-order cascade modulators realized by means of switched-capacitor circuits. It considers singlebit and multibit quantizers and draws a number of comparative remarks validated by time-domain behavioral simulations.