Manuel Delgado-Restituto

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved in the design of analog CMOS integrated circuits for the generation of chaotic behavior.

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCSs, PWL VCCSs, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCSs and PWL VCCSs are presented and applied to design a Chuas circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chuas circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chuas attractor by changing a bias current. >

A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression

This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.

High resolution CMOS current comparators: design and applications to current-mode function generation

This paper uses fundamental models to derive design conditions for maximum speed and resolution in CMOS transimpedance comparators. We distinguish two basic comparator architectures depending on whether the input sensing node is resistive or capacitive, and show that each type yields advantages for different ranges of input current. Then, we introduce a class of current comparator structures which use nonlinear sensing and/or feedback to combine the advantages of capacitive-input and resistive-input architectures. Two members of this class are presented demonstrating resolution levels (measured on silicon prototypes) in the range of pAs. They exhibit complementary functional features: one, the current steering comparator, displays better transient response in the very comparison function, while operation of the other, the current switch comparator, is easily extended to support systematic generation of nonlinear transfer functions in current domain. The paper explores also this latter extension, and presents current-mode circuit blocks for systematic generation of nonlinear functions based on piecewise-linear (PWL) approximation. Proposals made in the paper are demonstrated via CMOS prototypes in two single-poly CMOS n-well technologies: 2μm and 1.6μm. These prototypes show measured input current comparison range of 140 dB, resolution and offset below 10 pA, and operation speed two orders of magnitude better than that of conventional resistive-input circuits. Also, measurements from the PWL prototypes show excellent rectification properties (down to a few pAs) and small linearity errors (down to 0.13%).

Review of the State of the Art

This chapter reviews the state of the art of low-power TRXs for WBAN applications. The different proposals are categorized in three groups: narrow-band TRXs, usually compliant with WBAN standards; wide-band TRXs, most often employing proprietary signaling; and, for completeness, pulsed ultra wide-band TRXs.

A modular programmable CMOS analog fuzzy controller chip

We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule two input CMOS 1-/spl mu/m prototype which features an operation speed of 2.5 Mflips (2.5/spl times/10/sup 6/ fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm/sup 2/ including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.

Mixed-signal map-configurable integrated chaos generator for chaotic communications

This paper proposes a mixed-signal map-configurable chaos generator suitable for silicon integration, and makes an exhaustive analysis of its error sources and tolerance to the onset of saturation. The developed methodology has been applied in the design, embedded in a complete frequency-modulated differential-chaos shift keying (FM-DCSK) modem, of a chaos generator which achieves 10 bit resolution at a maximum clock frequency of 20 MHz, from a 3.3-V power supply.

Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/spl mu/m double-poly technology.

A chaotic switched-capacitor circuit for 1/f noise generation

A switched-capacitor circuit is reported for the generation of 1/f/sup y/ noise. The circuit is described by a chaotic first-order piecewise-linear discrete map which yields a hopping transition between regions of chaotic motions, and hence produces 1/f/sup y/ noise. Experimental results form a parasitics-insensitive prototype are included, demonstrating the circuit performance. >

Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.We present a 90-dB spurious-free dynamic range sigma-delta modulator M) for asymmetric digital subscriber line applications (both ADSL and ADSL ), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25- m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band ADSL and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within 0.85 and 0.80 LSB b , respectively. The modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the modulator.