David L. O'Meara

Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme

Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming / reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER) / Line Width Roughness (LWR); critical dimension uniformity (CDU); and profile in 3-dimensions for the resist trim / reformation etch is extremely aggressive. In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.

A spacer-on-spacer scheme for self-aligned multiple patterning and integration

To enable lithographic printing of ever smaller features, multipatterning techniques are increasingly being used in the semiconductor industry. These techniques are designed to extend 193nm immersion lithography, which is necessary to enable designs at 20nm or below. Multipatterning methods, however, are typically two to three times more expensive for each wafer than for a theoretical 193nm-immersion-based single exposure (assuming that 193nm immersion could be used to achieve the desired pitch). Moreover, extreme UV (EUV) lithography—a technology for the 5nm node that is expected to be available after 2020—is a costly option for high-volume production at major foundries and integrated device manufacturers (see Figure 1).1 At present, self-aligned quadruple patterning (SAQP) is the optimum technique for patterning of layers that require the most aggressive pitch shrink (such as fin formation and critical metal layers). In a standard SAQP stack, two hard mandrels are used alongside the appropriate etch stop and hardmask layers (see Figure 2). Integration of these components, however, is complex and involves several sacrificial layers that require multiple dry-etch and wet-etch steps. In response to this complexity, developers have so far made several attempts to simplify multipatterning processes, and to reduce costs and improve throughput.2, 3 We propose a low-cost alternative SAQP scheme that features no sacrificial layers, and which uses a spacer-on-spacer pitch-splitting strategy (see Figure 3). With our method, which requires careful selection of the underlying substrate, mandrel, and spacer materials, we can achieve a 25% reduction in cost Figure 1. Normalized wafer cost adder for different multipatterning techniques, according to internal TEL calculations. Numbers in the right hand column are multiples of the cost of single exposure patterning (e.g., LELE is 2.5 times the cost of SE). SAQP: Self-aligned quadruple patterning. EUV: Extreme UV. LELELE: Litho etch litho etch litho etch.