Ramana M. Malladi

Through-silicon vias enable next-generation SiGe power amplifiers forwireless communications

We feature a 0.35-µm SiGe BiCMOS technology (SiGe 5PAe) that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low-inductance ground to the package using through-silicon vias (TSVs) that results in a competitive solution for future multiband and multimode PA integration. The tungsten-filled, multifinger, bar-shaped TSV delivers more than a 75% reduction in inductance compared to a traditional wirebond. This enables higher frequency applications with a roughly 20% reduction in die area without compromising the technology reliability for use conditions in a low-cost plastic QFN (quad flat no leads) package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, its reliability, and its usefulness in a demanding WiMAX® (Worldwide Interoperability for Microwave Access) PA application.

A 0.35 μm SiGe BiCMOS technology for power amplifier applications

In this paper we introduce, a state-of-the-art SiGe BiCMOS power amplifier technology that features two NPNs with 40 GHz / 6.0 V & 27 GHz / 8.5 V (fT - BVceo) respectively, a novel low inductance metal ground through-silicon-via (TSV), integrated on a low-cost 0.35 μm lithography node with 3.3 V / 5.0 V dual-gate CMOS technology and high-quality passives on a 50 Ω.cm substrate.

SiGe BiCMOS technologies for power amplifier applications

Silicon-germanium (SiGe) BiCMOS technology has advanced in many areas. In this paper, we discuss and illustrate the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier applications. The experimental results for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented with focus on the 0.5 /spl mu/m SiGe BiCMOS node. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless power amplifier applications are considered.

Compact modeling of collector base junction space charge region transit time effect on noise in SiGe HBTs

This paper investigates the impact of collector-base space charge region (CB SCR) transport on RF noise in bipolar transistor using compact modeling. A model applicable to any compact models is derived and implemented using Verilog-A. Comparison with noise measurement on a SiGe HBT technology shows that overall the noise modeling results are much improved. The imaginary part of optimum generator admittance is slightly worse than without this effect.

Geometry scaling issues originated by extrinsic stress in SiGe HBTs

The influence of stress induced by shallow trench isolation (STI) on the geometry scaling of DC parameters in SiGe HBTs is studied. It is shown that smaller devices experience higher stress effect due to the STI than larger devices. In the presence of stress, the scaling of transfer current with geometry can not be fully accounted by separating it into area and perimeter components. STI stress effect is studied here, by varying emitter-STI spacing and emitter geometry parameters. Stress is shown to affect current gain and BVCEO as well. Based on the Vbe shift for smaller geometries, stress seen by the device is estimated.

Large Signal Modeling of High Efficiency SiGe HBTs for Power Amplifier Applications

Large-signal compact modeling of SiGe HBTs integrated into a new IBM BICMOS technology geared towards high-efficiency power amplifiers is described. The technology exhibits a record 73% PAE at 5.75 GHz in class AB operation. A scalable HiCUM model (high current model) is developed to accurately model the DC, small-signal and large-signal characteristics. Results of DC, fT characteristics, output power, PAE and AM-PM performance of the device are discussed in detail.

Influence of the Ge profile on VBE and current gain mismatch in Advanced SiGe BICMOS NPN HBT with 200 GHz fT

Transistor mismatch is a key parameter for the design and operation of advanced analog circuits. The paper presents for the first time data from several generations of BiCMOS technology nodes for VBE and current gain (beta) mismatch. The authors show that the 0.12 mum BiCMOS has a 3-a VBE mismatch of 0.63 mV-mum and beta mismatch of 0.24 %-mum. CBE NPNs have essentially the same but slightly lower mismatch than CBEBC NPNs. Very small and very long devices have increased mismatch, especially at high currents. The authors also present a physical model and experimental data showing the influence of the emitter-base Ge slope on the device mismatch

A high-injection transit-time model for heterojunction barrier effects in SiGe HBTs

A physics-based f/sub T/ model considering high-injection heterojunction barrier effects in SiGe HBTs is derived. It accurately captures f/sub T/ behavior at high J/sub C/, and offers better insight into the Kirk and barrier effect In SiGe HBTs.