Anthony J. Konecni

Integrated barrier/plug fill schemes for high aspect ratio Gb DRAM contact metallization

Abstract New contact fill integration schemes were developed for high aspect ratio Gb DRAM contact metallization. Integration schemes for both tungsten-plug contacts and aluminum-plug contacts were studied. For tungsten-plug contacts, various types of titanium liners and titanium nitride barriers were investigated and evaluated. These included collimated PVD (physical vapor deposition) titanium, ion metal plasma (IMP) titanium, and CVD (chemical vapor deposition) titanium liners; plasma enhanced CVD (PECVD) titanium nitride and plasma enhanced MOCVD (ECVD) titanium nitride barriers. The electrical results of 0.3 μm, 5:1 aspect ratio (AR) contact structures processed with a TiCl4-based CVD titanium liner and plasma enhanced CVD titanium nitride barrier show the lowest and the most tightly distributed contact parametrics. This is attributed to the conformal nature of the CVD process. In addition, the high titanium-deposition temperature, which leads to a simultaneous titanium silicide formation during the CVD titanium deposition process, may also have attribution to the low contact resistance and diode leakage obtained. In the case of aluminum-plug contacts, two different types of titanium nitride barriers (ECVD titanium nitride vs. silane-treated MOCVD titanium nitride) were evaluated and both showed comparable contact parametrics.

Integrated CVD-PVD Al plug processing for sub-half micron features

Abstract We have successfully integrated Al plugs into a 0.25- μ m CMOS flow using two different chemical vapor deposition (CVD) Al metallization process schemes. Both process schemes utilized CVD Al grown from dimethyl aluminum hydride (DMAH) followed by physical vapor deposition (PVD) Al–Cu deposition at a wafer temperature of less than 400°C. One process consisted of a 600-A CVD Al liner followed by PVD Al–Cu and in situ reflow. The second process involved deposition of 2000 A of CVD Al to fill the vias and blanket PVD Al–Cu to provide copper doping. Analysis of morphology, texture, and grain size revealed a strong dependence on the nucleation layer, with Ti nucleation layers demonstrating the smoothest Al morphology and strongest Al(111) preferred orientation. While the CVD TiN layers yielded a larger grain size than the PVD layers, Al films on CVD TiN had a random grain orientation with no preferred texture. While the reflow process produced repeatable void-free fill on contacts and vias with aspect ratios >3:1, the blanket process was prone to occasional voiding. Mean via and contact resistances for wafers processed through a 0.25- μ m CMOS flow using the CVD–PVD reflow process were 1.91 Ω and 1.56 Ω, respectively, with lower resistance and tighter distributions than W in both cases. For the contact level process, reverse bias diode leakage was comparable to W. Based on the blanket film properties, robust fill, and electrical performance, the CVD Al/PVD Al–Cu reflow process is a potential replacement for the current W plug process.