Anthony Leroy

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time.We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits.Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip

To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit time-division multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time. We propose an alternative solution based on spatial division multiplexing (SDM). This paper describes our design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM can be better adapted to NoCs than TDM in a specific context. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. A comparison is also performed with a state-of-the-art industrial reference NoC: Arteris.

Power breakdown analysis for a heterogeneous NoC platform running a video application

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized application mapping.

Design style case study for embedded multi media compute nodes

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on both (realtime) performance and energy consumption and forces designers to optimise all parts of their platform. In this experiment we focus on the different processor core design options for embedded platforms, including the effect of instruction memory hierarchy on the energy consumption. The results show that significant improvements for energy efficiency and/or performance over currently used RISC or VLIW processors can be achieved. We conclude, based on concrete data for a realistic application, that different styles, including both configurable hardware and instruction set processors, find their way into heterogeneous platforms and designers need to be aware of the trade-offs. Secondly, we show for the same application task that a heavily optimised instruction/configuration memory hierarchy can significantly reduce the energy consumption of this part, so it forms a crucial part of every energy aware design.

Quantitative Comparison of Switching Strategies for Networks on Chip

To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will integrate many processor nodes and memory units. To interconnect these IP nodes, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. One major problem consists in being able to compare choices and strategies in NoC design. To tackle this problem, we propose a complete highly configurable framework called Polymorpher which enables a quantitative comparison of the performance and energy consumption of different NoC communication component architectures. Our models are based on a set of basic VHDL communication components that can be reused for different designs. This common test-bed allows us to fairly and accurately compare different types of communication components in terms of energy consumption, delay and area. In particular, the framework enables easy instantiation and exploration of different types of routers. We have chosen to explore different switching strategies and parameters as an example of the possibilities offered by our tool. Our study compares quantitatively different switching techniques widely used in NoCs (store and forward, virtual cut through, wormhole) in terms of power consumption, area overhead and delay with a post lay-out gate-level simulation.