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Dive into the research topics where Adelina Shickova is active.

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Featured researches published by Adelina Shickova.


international conference on hardware/software codesign and system synthesis | 2005

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

Anthony Leroy; Pol Marchal; Adelina Shickova; Francky Catthoor; Frédéric Robert; Diederik Verkest

To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time.We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits.Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.


international reliability physics symposium | 2008

Reliability issues in MuGFET nanodevices

Guido Groeseneken; Felice Crupi; Adelina Shickova; Steven Thijs; Dimitri Linten; Ben Kaczer; Nadine Collaert; Malgorzata Jurczak

In this paper we review some recent results on reliability of MuGFET nanodevices with different gate stacks, including polycrystalline-Si/SiON as well as deposited metal gate/high-k stacks. In the first part we show how we can get information on the interface quality of the sidewall and top interface of the devices, by using an adapted charge pumping technique on gated diode structures. Then we compare the TDDB behavior of MuGFET and planar devices and we will show that if adequate processing is used, the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown for different gate voltages and temperatures. Next we discuss the Bias Temperature Instability (BTI) behavior of MuGFET CMOS devices. Novel interface passivation techniques as well as the impact of different dielectric nitridation techniques on BTI are discussed, showing similar BTI dependence on Nitrogen incorporated in MuGFET dielectrics as in planar devices. Finally we also discuss the ESD performance of MuGFET devices and we demonstrate that reasonable intrinsic ESD performance can be obtained, but achieving this desired ESD-robustness is found to be critically dependent on various design and process parameters. As a result the design of ESD protection for FinFET technology appears to be a challenging task for the future.


IEEE Electron Device Letters | 2007

On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

Eddy Simoen; Peter Verheyen; Adelina Shickova; Roger Loo; C. Claeys

The low-frequency noise of silicon pMOSFETs with embedded SiGe source/drain (S/D) regions is studied. The gate stack consists of HfSiON/SiO2 covered by a fully silicided gate electrode. S/D regions with different Ge content and thickness have been processed. It is shown that, while mobility and drive current are significantly enhanced by this strain-engineering approach, the 1/f noise is little affected, irrespective of the germanium content or thickness of the epitaxial SiGe S/D layers, i.e., the amount of compressive strain in the channel. From this, it is derived that, first of all, the embedded (S/D) processing does not degrade the gate-stack quality and that, second, no evidence of an intrinsic strain effect on the 1/f noise is observed here.


IEEE Electron Device Letters | 2007

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

Adelina Shickova; B. Kaczer; Peter Verheyen; G. Eneman; E.S. Andres; M. Jurczak; P. Absil; Herman Maes; G. Groeseneken

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation


real-time systems symposium | 2004

Design style case study for embedded multi media compute nodes

Andy Lambrechts; Tom Vander Aa; Murali Jayapala; Guillermo Talavera; Anthony Leroy; Adelina Shickova; Francisco Barat; Bingfeng Mei; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; Frédéric Robert; Jordi Carrabina Bordoll

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on both (realtime) performance and energy consumption and forces designers to optimise all parts of their platform. In this experiment we focus on the different processor core design options for embedded platforms, including the effect of instruction memory hierarchy on the energy consumption. The results show that significant improvements for energy efficiency and/or performance over currently used RISC or VLIW processors can be achieved. We conclude, based on concrete data for a realistic application, that different styles, including both configurable hardware and instruction set processors, find their way into heterogeneous platforms and designers need to be aware of the trade-offs. Secondly, we show for the same application task that a heavily optimised instruction/configuration memory hierarchy can significantly reduce the energy consumption of this part, so it forms a crucial part of every energy aware design.


international reliability physics symposium | 2009

The role of nitrogen in HfSiON defect passivation

Robert O'Connor; Marc Aoulaiche; Luigi Pantisano; Adelina Shickova; Robin Degraeve; Ben Kaczer; Guido Groeseneken

In this work we examine the effect of nitrogen incorporation on the defect generation behavior in HfSiON gate dielectric layers. We show that nitrogen effectively passivates pre-existing defects in the HfSiO, but the effect is quickly reversed during stress leading to high levels of SILC and NBTI


Microelectronics Reliability | 2007

NBTI reliability of Ni FUSI/HfSiON gates: effect of silicide phase

Adelina Shickova; Ben Kaczer; A. Veloso; Marc Aoulaiche; Michel Houssa; Herman Maes; Guido Groeseneken; Jorge Kittl

Abstract In this work, we investigate the negative bias temperature instability (NBTI), when Ni-rich (Ni 2 Si and Ni 31 Si 12 ) silicides are used as gate electrodes on HfSiON and compare them to Ni mono-silicide (NiSi). The study also investigates the influence of increased pre-metal deposition (PMD) temperature and decreased silicide thickness on NBTI. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant differences in intrinsic NBTI behavior are found for devices with different Ni silicide gate electrodes. In addition, we performed an Arrhenius study showing similar activation energies, indicating that no favorable conditions for dielectric degradation are created by the increased amount of Ni.


Microelectronic Engineering | 2007

Dielectric quality and reliability of FUSI/HfSiON devices with process induced strain

Adelina Shickova; Ben Kaczer; Eddy Simoen; Peter Verheyen; Geert Eneman; Malgorzata Jurczak; P. Absil; Herman Maes; Guido Groeseneken


214th ECS Meeting | 2008

Trapping in 1nm EOT high-k / MG

M. B. Zahid; Luigi Pantisano; Robin Degraeve; Marc Aoulaiche; Lionel Trojman; I. Ferain; E. San Andrés; Adelina Shickova; Robert O'Connor; Guido Groeseneken; Marc Heyns; Stefan De Gendt


Archive | 2006

Dielectric breakdown study of multi-gate devices

Adelina Shickova; Nadine Collaert; Rita Rooyackers; An De Keersgieter; Thomas Kauerauf; M. Jurczak; Ben Kaczer; Guido Groeseneken

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Ben Kaczer

Katholieke Universiteit Leuven

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Diederik Verkest

Vrije Universiteit Brussel

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Guido Groeseneken

Katholieke Universiteit Leuven

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Anthony Leroy

Université libre de Bruxelles

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Frédéric Robert

Université libre de Bruxelles

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Herman Maes

Katholieke Universiteit Leuven

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Peter Verheyen

Katholieke Universiteit Leuven

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Bingfeng Mei

Katholieke Universiteit Leuven

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