Arash Hazeghi

Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer.

Carbon nanotube circuits in the presence of carbon nanotube density variations

Carbon nanotubes (CNTs) are grown using chemical synthesis. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of carbon nanotube field effect transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variations is presented based on experimental data extracted from aligned CNT growth. This model is used to quantify the impact of such variations on design metrics such as noise margin and delay variations of CNFET circuits. Finally, we analyze correlation that exists in aligned CNT growth, and demonstrate how the reliability of CNFET circuits can be significantly improved by taking advantage of such correlation.

Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling

The theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs) is examined by means of a general ballistic model. A novel approach is used to treat the SBs at the metal-nanotube contacts as mesoscopic scatterers by modifying the distribution functions for carriers in the channel. Noticeable current reduction is observed compared to previous ballistic models without SBs. Evanescent-mode analysis is used to derive a scale length and the potential profile near the contacts for radially symmetric CNFET structures. Band-to-band tunneling current and ambipolar conduction are also treated. The effects of different device geometries and different nanotube chiralities on the drain-current are studied using this simple model. Quantum conductance degradation due to SBs is also observed

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations

Variations in the spatial density of carbon nanotubes (CNTs), resulting from the lack of precise control over CNT positioning during chemical synthesis, is a major hurdle to the scalability of carbon nanotube field effect transistor (CNFET) circuits. Such CNT density variations can lead to non-functional CNFET circuits. This paper presents a probabilistic framework for modeling the CNT count distribution contained in a CNFET of given width, and establishes the accuracy of the model using experimental data obtained from CNT growth. Using this model, we estimate the impact of CNT density variations on the yield of CNFET very large-scale integrated circuits. Our estimation results demonstrate that CNT density variations can significantly degrade the yield of CNFETs, and can be a major concern for scaled CNFET circuits. Finally, we analyze the impact of CNT correlation (i.e., correlation of CNT count between CNFETs) that exists in CNT growth, and demonstrate how the yield of a CNFET storage circuit (primarily limited by its noise immunity) can be significantly improved by taking advantage of such correlation.

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Three key advances in device technology must be made to realize the potential of carbon nanotube transistors: (1) aligned CNT density of ≥200 CNT/µm on a wafer scale, (2) stable p- and n-type doping on the same wafer with control over the doping level, (3) low resistance metal to CNT contact at short (<20 nm) contact length. CNFET technology has now advanced to a point where large scale circuit level demonstration can be contemplated. This is made possible by advances in wafer-scale CNT growth, multiple CNT transfer, and imperfection-immune design techniques to overcome mis-positioned CNTs [11] and m-CNTs (e.g. VMR [18–19] and ACCNT [27]). In order to minimize CNT-specific variations (e.g. CNT count variations [45]), circuit design techniques co-optimized with process technology will play an important role. In the near future, CNFET circuit performance demonstration at GHz clock speed with the requisite device density is expected.

An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements.

We have developed a highly sensitive integrated capacitance bridge for quantum capacitance measurements. Our bridge, based on a GaAs HEMT amplifier, delivers attofarad (aF) resolution using a small AC excitation at or below k(B)T over a broad temperature range (4-300 K). We have achieved a resolution at room temperature of 60 aF/√Hz for a 10  mV ac excitation at 17.5 kHz, with an improved resolution at cryogenic temperatures, for the same excitation amplitude. We demonstrate the utility of our bridge for measuring the quantum capacitance of nanostructures by measuring the capacitance of top-gated graphene devices and cleanly resolving the density of states.

Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling

The theoretical performance of Carbon Nanotube Field Effect Transistors (CNFETs) with Schottky barriers is examined by means of a ballistic model. A novel approach is used to treat the Schottky barriers at the metal-nanotube contacts as mesoscopic scatterers. Evanescent-mode analysis is used to derive a length-scale and potential profile for the device. Noticeable current reduction is observed compared to previous ballistic models without Schottky barriers. The effects of device geometry, nanotube diameter and chirality as well as Schottky barrier height on the drain current are studied. Quantum conductance degradation due to Schottky barriers is also observed.

Graphitic interfacial layer to carbon nanotube for low electrical contact resistance

Graphitic interfacial layer is used to wet the surface of carbon nanotube and dramatically lower the contact resistance of metal to metallic single-wall carbon nanotube (m-CNT). Using Ni-catalyzed graphitization of amorphous carbon (a-C), the average resistance of metal/m-CNT is reduced by 7X compared to the same contact without the graphitic layer. Small-signal conductance measurements from 77K to 300K reveal the effective contact improvement.

Carbon Nanotube Device Modeling and Circuit Simulation

The development of new technology requires tools at all levels of abstraction. Modeling tools for detailed calculations of the energy band diagrams and device current–voltage characteristics [1] are essential first steps for device physics understanding. At the same time, modeling tools at higher levels of abstraction are required for device design space exploration and circuit design. As an example, for Si CMOS technology, industry-standard tools such as PISCES [2] and SPICE [3] are essential for device design and circuit simulation, respectively. Higher level abstraction tools [4] are used to describe and synthesize circuits at the system level. In this chapter, we describe the development of a device-level model [5] that can be used as a rapid device design space exploration tool (an independent and parallel effort on SWNT-FET modeling can be found in [6]). It is simple enough to be run in a mixed-mode device/circuit simulation environment so that circuit issues can be studied at the device design level. We also describe the development of a circuitcompatible, compact device model [7] capable of large-scale circuit simulations. Using this circuit-compatible device model for SPICE, circuits consisting of a few hundred carbon nanotube transistors can be simulated.

Erratum: “An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements” [Rev. Sci. Instrum. 82, 053904 (2011)]

Arash Hazeghi, Joseph A. Sulpizio, Georgi Diankov, David Goldhaber-Gordon, and H. S. Philip Wong Citation: Rev. Sci. Instrum. 82, 129901 (2011); doi: 10.1063/1.3665097 View online: http://dx.doi.org/10.1063/1.3665097 View Table of Contents: http://rsi.aip.org/resource/1/RSINAK/v82/i12 Published by the AIP Publishing LLC.