van der Jd Johan Tang

Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator

A 5-GHz quadrature LC oscillator has been realized, in which the two LC stages are coupled with phase shifters. Analysis on the behavioral level shows that an N-stage LC oscillator is optimally coupled when each stage is connected with phase shifters providing /spl plusmn/180/spl deg//N phase shift. Simulation of the 5-GHz two-stage quadrature LC oscillator reveals a 4.3-dB reduction in phase noise compared to a quadrature LC oscillator without phase shifters. Measurements of the 5-GHz quadrature LC oscillator, made in a 30-GHz f/sub T/ process, show a phase noise lower than -113 dBc/Hz, with a resonator quality factor of only 4 and an oscillator core power dissipation of 21.2 mW.

A 9.8-11.5 GHz quadrature ring oscillator for optical receivers

A 9.8-11.5 GHz quadrature ring oscillator for use in the data clock recovery circuit of optical receivers has been realized in a BiCMOS technology with 30 GHz cut-off frequency. The circuit implementation of the oscillator uses active inductors which provide isolation between the oscillator and cascaded circuits such as buffers and flip-flops. Carrier to noise ratios better than 94 dBc/Hz at 2 MHz offset are measured with 75 mW dissipation and 2.7 V supply voltage. The realized quadrature oscillator achieves a state of the art oscillation frequency over transistor cut-off frequency ratio of 0.38.

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS

The design of a multi-band low noise amplifier (LNA) is the first obstacle towards the design of a multi-standard receiver. In this paper, an approach for the design of a multi-band LNA for DECT and Bluetooth is presented. The formula for a minimal noise factor of a LNA, that takes into account the finite quality factor of the inductors is derived and the full design procedure that facilitates the design of a fully integrated LNA is given. The main advantages of the presented multi-band LNA are: high level of integration, reduced chip area by using only one integrated inductor, while the other is implemented as a bond-wire, input matching at two frequencies while having low noise figure, moderate voltage gain and good linearity. In DECT mode the simulated LNA performance is: NF = 2.2 dB, gain = 17 dB, IIP3 = 0.5 dBm, with a current of 8 mA, while in Bluetooth mode the LNA achieves: NF = 2.3 dB, gain = 15 dB, IIP3 = 3 dBm, with a current of only 4 mA.

Intermodulation products in the EER technique applied to class-E amplifiers

Envelope elimination and restoration is a relatively old but attractive transmitter technique for high efficiency linear amplification of variable envelope RF signals. EER employs switching mode power amplifiers, which are extremely nonlinear but efficient, and the concept of supply voltage modulation to achieve linear performance. The bandwidth limitations in the envelope modulation path will have a strong impact on performance of the whole EER system. This paper derives analytic relationships between the transfer function in the envelope path of the EER system and IMD products in the output signal. The derived expressions are of generic character and can be used for an arbitrary transfer function in the envelope path. An estimation of the theoretical limit for IMD levels in the EER system based on the class-E amplifier is given.

Low voltage, low power folded-switching mixer with current-reuse in 0.18 /spl mu/m CMOS

The scaling of the CMOS technologies has a great impact on analog design. The most severe consequence is a reduction of the voltage supply. In this article, a new low-voltage folded-switching mixer with current-reuse, which operates at 1 V supply voltage, is discussed. The main advantages of the introduced mixer topology are: a high voltage gain, a low noise figure, an operation at low supply voltages and flexibility in terms of mixer redesign for operation at different supply voltages. In order to alleviate the mixer design for different set of specifications and to provide a designer with a mixer design procedure, insight into mixer operation is given analyzing gain, noise figure and linearity. The mixer is designed in 0.18 /spl mu/m CMOS technology. Taking into account the obtained simulation results at a supply voltage of 1 V (gain = 9 dB, NF = 12 dB, IIP3 = -1 dBm) and with a power consumption of 2.8 mW, the presented folded-switching mixer with current-reuse outperforms many of, so far, published CMOS mixers.

A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion

This paper deals with the system and circuit-level aspects of an ultra-low-power robust wireless node for an asymmetric wireless link. A single building block TX front-end for a frequency hopping spread spectrum (FHSS) transmitter implemented in silicon-on-anything (SOA) bipolar technology is presented. It is realized with a directly modulated RF cascoded Colpitts power voltage-controlled oscillator (VCO), a frequency locked loop for center frequency calibration, and a digital pre-distortion algorithm for accurate frequency bins synthesis. The TX front-end draws only 1 mA at -18 dBm output power. By combining digital system techniques for frequency hopping and merging the VCO and the power amplifier (PA), a robust solution is obtained for indoor ultra-low-power wireless links. The proposed pre-distortion concept allows reduction of the hardware complexity, while the combination of a cascode output buffer and a common-collector Colpitts VCO allows us to reduce the complete FHSS front-end to a single building block that directly drives the antenna through a balun. A dedicated digital algorithm on the receiver side reduces the center frequency offset from a maximum value of 8.2 MHz to less than 8 ppm avoiding the use of any crystal on the transmitter side. Precision in the hopping synthesis is obtained by employing a ST-DFT based demodulator with differential encoding and an offset sending technique. The novel FHSS-predistortion concept has been verified by realizing a full wireless link that achieves a bit error rate better than 1.1% at -25 dBm output power while transmitting across an 8 meters indoor non-line-of-sight (NLOS) path.

A low-phase-noise reference oscillator with integrated pMOS varactors for digital satellite receivers

A low-phase-noise LC reference oscillator (RO) for use in digital satellite receivers is described. This RO is an essential building block of a double-loop wide-band tuning system that reduces the phase noise of integrated quadrature voltage-controlled oscillators (VCOs) required for zero-IF receivers. In order to achieve a high degree of integration the RO is implemented using integrated varactors. Three varactor options which are available in a standard 11-GHz f/sub t/ bipolar technology are investigated: the p-n junction of an NPN, an active varactor circuit, and a pMOS varactor. Experimental results show that the integrated pMOS varactor combined with external inductors is the preferred choice to implement the resonator of the low-phase-noise RO. The achieved tuning range is 225-310 MHz. Carrier-to-noise levels of more than 87 dBc/Hz at 10-kHz offset are measured. The performance is realized with a RO dissipation of 14 mW at a supply voltage of 3.5 V.

Design of Flexible RF Building Blocks-A Method for Implementing Configurable RF Transceiver Architectures

In todays world, new communication standards evolve fast, putting a significant burden on set makers and RFIC designer houses to bring integrated and cheap solutions quickly into the market place. The shift towards flexible RF systems that can support a range of applications via adjustability and re-usability is a solution to these problems. In this paper an approach for design of adjustable and programmable RF building blocks is represented as a basis for adding flexibility and multi-standard capability to transceiver front-ends. The design approach is based on generating a library of reusable, configurable RF building blocks and a structured, economical method for implementing transceivers using these building blocks

An ultra-low power predistortion-based FHSS transmitter

In the new era of personal communications, the energy available for a wireless node is the limiting factor. Furthermore wireless links should be robust even in the harsh indoor environment where fading, attenuation and interferences can be severe. Spread-spectrum techniques are largely used to have a robust link, while frequency-hopping (FH) is the most suitable for low data-rate applications. Unfortunately state-of-the-art FH systems are still far too complex and too power hungry to be implemented in a self contained wireless node. The proposed architecture simplifies considerably the hardware requirements for the hopping synthesizer achieving a current consumption of only 900 muA (excluding the output buffer) from a 1.8 V power supply

A DECT/Bluetooth multi-standard front-end with adaptive image rejection in 0.18 /spl mu/m CMOS

A DECT/Bluetooth multi-standard front-end with adaptive image rejection is described. The front-end is designed and simulated in 0.18 /spl mu/m CMOS technology. Using a multi-band LNA with zero external components full integration of the front-end is achieved. In high image-reject DECT mode it has a NF of 10 dB consuming a current of 47 mA, while in low image-reject DECT mode a NF of 5 dB is obtained with a current of 39 mA. In high image-reject Bluetooth mode the front-end achieves a NF of 10 dB consuming a current of 39 mA and in low image-reject Bluetooth mode it has a NF of 5 dB using a current of 31 mA. Applying adaptive image rejection the power consumption is reduced 20%, the NF is improved 50% and the gain improves 30%, while the chip area is negligibly increased compared to the total chip area occupied by the front-end.