Johan van der Tang

A 40nm wideband direct-conversion transmitter with sub-sampling-based output power, LO feedthrough and I/Q imbalance calibration

In the last decade the amount of digital data generated in connection with digital devices such as cameras, media players and high-definition TVs has seen a significant growth. This requires tuners for home networking such as MoCA with increasingly large bandwidth. Though advanced CMOS technology allows for the design of high-speed circuits and systems that can meet the need for more bandwidth, 40nm feature sizes and beyond introduce new challenges in analog circuit design [1]. Moreover, dependence on environmental conditions of device spread and matching performance with parasitic coupling can drastically reduce the overall system performance.

ULTRA-LOW POWER FREQUENCY-HOPPING SPREAD SPECTRUM TRANSMITTERS AND RECEIVERS

This paper examines system and circuit design techniques for a “microWatt node” operating at power level low enough to enable the use of an energy scavenging source. While several architectures have been investigated in order to reduce the overall system power consumption, none of them is able to guarantee robustness of the link and ultra-low power consumption at the same time. A survey of the most advanced architectures meant for ultra-low power transceivers is described. Advantages and drawbacks of all these systems are discussed and the reasons for an architecture based on Frequency-Hopping (FH) Spread-Spectrum (SS) are discussed. Finally a novel FH synthesizer based on digital pre-distortion architecture is proposed in order to reduce the power consumption of the hopping synthesizer. The FH architecture together with a frequency offset robust demodulation technique allows a reduction by a factor 8 of the power consumption compared to the state-of-the-art synthesizers. Furthermore, a single RF block front-end is obtained combining together the VCO and the PA. The novel RF front-end can be directly coupled to the antenna through a balun and the system is able to deliver -18 dBm output power on 50 Ω load at 1 mA current consumption (2 V power supply). To prove the new synthesizer principle a communication link in the 902-928 MHz ISM band has been set-up. The receiver, mainly software with a flexible RF front-end, adopted a ST-DFT demodulation algorithm and achieved a BER smaller than 1.1% at -25 dBm output power, with TX and RX antennas placed at 8 meters distance in a NLOS condition and in a common office environment.

A 375 mW, 2.2 GHz signal bandwidth DAC-based transmitter with an in-band IM3 < −58 dBc in 40 nm CMOS

A 40 nm DAC-based CMOS wideband transmitter (WBTX) for cable applications is presented. It has a 2.2 GHz signal bandwidth and exhibits an in-band IM3 of less than -58 dBc. The WBTX consists of a current-steering DAC with digital sinc equalization and roll-off compensation. By implementing high-speed, feed-forward pipelined digital logic, the DAC sampling rate extends to 5 GHz. The WBTX can deliver up to +11 dBm of output power while consuming only 375 mW. The WBTX occupies 1.65 mm2 of area.

Architectures and synthesizers for ultra-low power fast frequency-hopping WSN radios

1 Introduction. 1.1 Application field. 1.2 System requirements. 1.3 Energy scavenging techniques. 1.4 General wireless node requirements. 1.5 State of the art. 1.6 The objectives of this book. 1.7 Outline of the book. 2 System-Level and Architectural Trade-offs. 2.1 Modulation schemes for ultra-low power wireless nodes. 2.2 Optimal Data-rate. 2.3 Transmitter architectures. 2.4 Receiver architectures. 2.5 Conclusions. 3 FHSS Systems: State-of-the-art and Power Trade-offs. 3.1 Synchronization. 3.2 State-of-the-art Frequency Hopping Spread Spectrum (FHSS) systems. 3.3 Frequency Hopping (FH) synthesizer architectures. 3.4 Specifications for ultra-low-power frequency-hopping synthesizers. 3.5 PLL power estimation model. 3.6 Direct Digital Frequency Synthesizer (DDFS) power estimation model. 3.7 Summarizing discussion. 3.8 Conclusions. 4 A One-way Link Transceiver Design. 4.1 General guidelines for transmitter design. 4.2 Transmitter architecture. 4.3 Receiver architecture. 4.4 Implementation and experimental results. 4.5 Conclusions. 5 A Two-way Link Transceiver Design. 5.1 Transmitter design general guidelines. 5.2 Transmitter architecture. 5.3 Synthesizer design. 5.4 Generation of a 288-MHz reference clock. 5.5 Receiver design at system level. 5.6 Simulation and experimental results. 5.7 Conclusions. 6 Summary and conclusions. 7 Acronyms. Appendices. A Walsh based harmonic rejection sensitivity analysis. References.