Arnab Biswas

Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design

In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (LG1) with a total overlap of the back gate over the channel region (LG2). A potential well is created by biasing the back gate (VG2) in accumulation while the front gate (VG1) is in inversion. Holes from the p+ source are injected by the forward-biased source/channel junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated.

An innovative band-to-band tunneling analytical model and implications in compact modeling of tunneling-based devices

In this paper, an analytical band-to-band tunneling model is proposed, validated by means of drift-diffusion simulation and comparison with experimental data, implemented in Verilog-A, and finally proven with SPICE simulator through simulation of circuits featuring tunneling diodes. The p-n junction current calculation starts from a non-local Band-to-Band tunneling theory including the electron-phonon interaction and therefore it is particularly suited for indirect semiconductor materials such as silicon- or germanium-based interband tunneling devices.

A tunneling field-effect transistor exploiting internally combined band-to-band and barrier tunneling mechanisms

This letter proposes a hybrid abrupt switch principle and a corresponding device architecture that combines quantum mechanical band-to-band and barrier tunneling mechanisms. The device overcomes the intrinsically low on-current (I-ON) of conventional tunnel field-effect transistors (TFETs) and the 60 mV/dec subthreshold swing limitation of metal-oxide-semiconductor FETs at room temperature. The device principle and characteristics are studied through two-dimensional numerical simulations. The predicted performance of such hybrid TFET architecture, implementing an ultrathin (0.5 nm) tunneling dielectric between metal source and silicon channel are: average SS values as low as 43 mV/dec, I(ON similar to)49.3 mu A/mu m, and I-ON/I(OFF similar to)10(7). (c) 2011 American Institute of Physics. [doi:10.1063/1.3569760]

New tunnel-FET architecture with enhanced I ON and improved Miller Effect for energy efficient switching

Tunneling Field Effect Transistors (TFET) are promising devices to respond to the demanding requirements of future technology nodes. The benefits of the TFETs are linked to their sub-60mV/decade sub-threshold swing, a prerequisite for scaling the supply voltage well below 1V. Main research efforts are currently dedicated to improving the on current (ION) level in a TFET. However, from the circuit point of view the device capacitances are equally important. It is known that the drain-to-gate capacitance in a TFET is almost equal to the gate capacitance in moderate and strong inversion regimes. Due to enhanced Miller Effect, they are known to exhibit large over/undershoot in transient operation as compared to CMOS. Therefore, the effort on improving ION should be simultaneous to an effort of reducing the Miller capacitance (CMILLER). This work proposes a new architecture which addresses both these issues.

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursued approaches to achieve such a subthermionic subthreshold swing consist in alternative carrier injection mechanisms, like quantum mechanical band-to-band tunneling (BTBT) in Tunnel FETs or abrupt phase-change in metal-insulator transition (MIT) devices. The strengths of the BTBT and MIT have been combined in a hybrid device architecture called phase-change tunnel FET (PC-TFET), in which the abrupt MIT in vanadium dioxide (VO2) lowers the subthreshold swing of strained-silicon nanowire TFETs. In this work, we demonstrate that the principle underlying the low swing in the PC-TFET relates to a sub-unity body factor achieved by an internal differential gate voltage amplification. We study the effect of temperature on the switching ratio and the swing of the PC-TFET, reporting values as low as 4.0 mV/decade at 25 °C, 7.8 mV/decade at 45 °C. We discuss how the unique characteristics of the PC-TFET open new perspectives, beyond FETs and other steep-slope transistors, for low power electronics, analog circuits and neuromorphic computing.

Conformal mapping based DC current model for double gate tunnel FETs

In this work, the conformal mapping technique is applied to obtain an analytical closed form solution of the 2D Poissons equation for a double-gate Tunnel FET. The generated band profiles are accurate in all regions of device operation. Furthermore, the current levels are estimated by implementing the non-local band-to-band tunneling model from Synopsys Sentaurus TCAD. A good agreement with simulations for varying device parameters is demonstrated and the advantages and limitations of the new modeling approach are investigated and discussed.

Study of fin-tunnel FETs with doped pocket as capacitor-less 1T DRAM

In this work we propose and validate by experimentally calibrated simulations a silicon Tunnel FET(TFET) based capacitorless DRAM cell, implemented as a fully-depleted FinFET with CMOS compatible process. The devices have a conventional FinFET structure except for a p+ (for n-type TFET) doped pocket of length LPKT and doping NPKT between the intrinsic channel and the (n++) drain. This doped pocket creates a necessary condition to store holes injected from the source-to-body junction. In [1], there was a need to induce a potential well in order to store the excess charges; whereas in the present case a potential well is permanently present due to the doped pocket. The drain voltage is used as a control voltage to either fill the potential well with carriers (WRITE “1”) by attracting holes from the p++ source or repel them to empty the well of carriers (WRITE “0”). In contrast with the SOI Z-RAM® there is no need of impact ionization to create/inject the hole charge in the device body, the holes being injected by the forward-bias p+i junction, which significantly improves the device reliability. Measurements on FDSOI TFET devices as reported in [1,2] were performed at elevated temperatures and used to calibrate the non-local band-to-band (B2B) tunnelling model in Sentaurus TCAD [3]. The retention characteristics of the proposed memory cell is simulated at an elevated temperature of 85°C and is shown to be not degrading at higher temperature as is the case in conventional capacitorless DRAMs [4].

Compact modeling of DG-Tunnel FET for Verilog-A implementation

In this work, a compact model based on an analytical closed form solution of the 1D Poissons equation for a double-gate Tunnel FET is derived. Furthermore, the current levels are estimated by implementing an algorithm based on the Kanes band-to-band tunneling model. A good agreement with numerical simulations for varying device parameters is demonstrated and the advantages and limitations of the modeling approach are investigated and discussed. The model is implemented in a Verilog-A based circuit simulator and basic circuit blocks like an inverter, a 2-bit half adder and a 15 stage ring oscillator are simulated to demonstrate the capabilities of the model. The switching energy of a Tunnel FET based circuit block is studied with Vdd scaling revealing interesting aspects of Tunnel FET circuit behavior.

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET performance. In this work, a simple physics-based compact analytical model has been developed for the junction steepness as a function of the doping concentration and the maximum electric field at the junction. Using the underlying physics, we report a novel yet simple method to estimate the lateral junction steepness using only the I-V measurements on a p+-i- n+ tunnel diode test structure fabricated on the same wafer as the TFET with common process steps. Assuming that doping concentration, Si thin-film thickness, and buried-oxide thickness are known from the fabrication process, this algorithm uses the maximum electric field extracted from the I-V measurements and applies the analytical model to estimate the junction steepness. It has been observed that the estimations based on this method have a maximum deviation of sub-0.2 nm/decade from the actual junction steepness of the investigated devices.