Wladyslaw Grabinski

Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS, allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-sectional cores on bulk Si substrate using optical lithography, hard mask/spacer technology, and local oxidation. ≈0.8 GPa uniaxial tensile stress was measured on the buckled dual nanowires using micro-Raman spectroscopy. The buckled multigate dual Si nanowires show excellent electrical characteristics, e.g., 62 mV/decade and 42% low-field electron mobility enhancement due to uniaxial tensile stress in comparison to the non-strained device, all at VDS = 50 mV and 293 K.

Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

Multi-gate architectures such as gate-all-around (GAA) Si nanowires are the promising candidates for aggressive CMOS downscaling due to the immunity to the issues regarding short channel effect, improved subthreshold slope and optimized power consumption. On the other hand, Si nanowires represent excellent mechanical properties e.g. yield strength of 10±2% [1] in comparison to 3.7% for bulk Si [2], a strong motivation to be used as interesting exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels [3]–[5] or local band-gap modulation using >4 GPa uniaxial tensile stress in suspended Si channels to enhance band-to-band tunneling current in multi-gate Tunnel-FETs [6], all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels.

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET performance. In this work, a simple physics-based compact analytical model has been developed for the junction steepness as a function of the doping concentration and the maximum electric field at the junction. Using the underlying physics, we report a novel yet simple method to estimate the lateral junction steepness using only the I-V measurements on a p+-i- n+ tunnel diode test structure fabricated on the same wafer as the TFET with common process steps. Assuming that doping concentration, Si thin-film thickness, and buried-oxide thickness are known from the fabrication process, this algorithm uses the maximum electric field extracted from the I-V measurements and applies the analytical model to estimate the junction steepness. It has been observed that the estimations based on this method have a maximum deviation of sub-0.2 nm/decade from the actual junction steepness of the investigated devices.

Determining MOSFET Parameters in Moderate Inversion

Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.