Nilay Dagtekin

Ultra low power: Emerging devices and their benefits for integrated circuits

In this paper we analyze and discuss the characteristics and expected benefits of some emerging device categories for ultra low power integrated circuits. First, we focus on two categories of sub-thermal subthreshold swing switches Tunnel FETs and Negative Capacitance (NC) FETs and evaluate their potential advantages for digital and analog design, compared to CMOS. Second, we investigate the combined low power and novel integrated functionality in some hybrid Nano-Electro-Mechanical (NEM) devices: the Resonant Body (RB) Fin FET for nW time reference ICs and dense arrays of Suspended Body (SB) Double Gate (DG) Carbon Nanotube (CNT) FET for low power analog/RF and integrated sensor arrays.

ARMADILLO: a multi-purpose cryptographic primitive dedicated to hardware

This paper describes and analyzes the security of a general-purpose cryptographic function design, with application in RFID tags and sensor networks. Based on these analyzes, we suggest minimum parameter values for the main components of this cryptographic function, called ARMADILLO. With fully serial architecture we obtain that 2923 GE could perform one compression function computation within 176 clock cycles, consuming 44 µW at 1MHz clock frequency. This could either authenticate a peer or hash 48 bits, or encrypt 128 bits on RFID tags. A better tradeoff would use 4030 GE, 77 µW of power and 44 cycles for the same, to hash (resp. encrypt) at a rate of 1.1 Mbps (resp. 2.9 Mbps). As other tradeoffs are proposed, we show that ARMADILLO offers competitive performances for hashing relative to a fair Figure Of Merit (FOM).

Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

Impact of Super-Linear Onset, Off-Region Due to Uni-Directional Conductance and Dominant

This paper investigates the consequences of several distinctive device characteristics of tunnel FETs (TFET), namely super-linear onset, uni-directional conduction, and the dominant gate-drain capacitance, regarding the energy consumption, propagation delay, and noise resilience. Simulations have shown that these TFET specific characteristics have a detrimental effect on the dynamic response. We also report that their impact remains significant when operating voltage is scaled. Thus device level optimizations are required to eliminate these attributes to take full advantage of TFETs small subthreshold swing and low voltage operation.

\mathrm{C}_{\text {GD}}

In this paper, an analytical band-to-band tunneling model is proposed, validated by means of drift-diffusion simulation and comparison with experimental data, implemented in Verilog-A, and finally proven with SPICE simulator through simulation of circuits featuring tunneling diodes. The p-n junction current calculation starts from a non-local Band-to-Band tunneling theory including the electron-phonon interaction and therefore it is particularly suited for indirect semiconductor materials such as silicon- or germanium-based interband tunneling devices.

on Performance of TFET-Based Circuits

This paper presents experimental results regarding optical and electrical characteristics of a partially gated p-i-n structure that has an extension in the channel region coated with transparent material. The correlation between band to band tunneling and photo current is discussed. Four main phenomena are observed under illumination: (1) negative transconductance can be obtained under reverse bias conditions (2) the off current is governed by the photocurrent and subthreshold slope is degraded (3) a kink in the saturation current appears in the output characteristics (4) the light sensitivity of the transconductance in P mode operation can be tuned with the back gate bias.

An innovative band-to-band tunneling analytical model and implications in compact modeling of tunneling-based devices

Silicon-based partially gated tunnel FETs are characterized under optical and electrical excitation. Most significant outcomes of the experiments are (1) unique characteristics, namely, light induced negative transconductance and optically tunable output resistance (photo-resistor), (2) phototransistor operation that is attained when back-gate is used to store optically generated carriers which in return modulate the transconductance of the transistor in on-state. Simulation results show that the investigated devices have the potential to give rise to new circuit topologies exploiting interaction between light and band-to-band tunneling processes, and improve the area efficiency of pixel sensors owing to their optical gain and charge storage mechanism.

Investigation of partially gated Si tunnel FETs for low power integrated optical sensing

This paper presents the first energy efficient highly compact concept of active pixel sensor built with a single partially-gated tunnel FET (TFET). Experimental results show that the transistor characteristics of the investigated TFETs are nonlinearly modulated by optical excitation and a transistor gain that is a function of irradiance and bias conditions is reported for the first time. A memory effect is observed and exploited when the backgate is used as a secondary gate to control charge storing mechanism in the body, similarly to backside illuminated pixels. Compared to CMOS, 1T-TFET pixel offers high sensitivity (detection limit <; 2pW/μm2 in visible light), low power operation, improved temperature stability (validation at 70°C) and high compactness (1T architecture with pixel size of ~10×1μm2 in this work).

Partially gated lateral tunnel field effect transistor for optical applications

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supply voltage reduction, and the rising leakage currents that directly affect the switching ratio between the ON and OFF states. At present, the available field-effect transistors (FETs) in the CMOS integrated circuits require at room temperature at least 60 mV of gate voltage to increase the current by one order of magnitude. Recent publications have highlighted the need for alternative devices providing better ON-OFF switching performance. Tunneling FETs are very promising devices to respond to the demanding requirements of future scaled silicon technology nodes. The paper reviews recent compact modeling of homojunction TFET devices.

Energy efficient 1-transistor active pixel sensor (APS) with FD SOI tunnel FET

In this work, we show that through appropriate optimization of the Ge EHBTFET it is possible to achieve superior static characteristics for low supply voltage applications, when compared to a doublegate Ge MOSFET with similar geometry. The tool used to perform the simulations in this paper is Synopsys Sentaurus Device E-2010.12.