W. T. Holman

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

On-Chip Characterization of Single-Event Transient Pulsewidths

A new on-chip single-event transient (SET) test structure has been developed to autonomously characterize the widths of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 mum technology and also indicate that the measurement granularity rapidly scales down with technology. Laser tests were used to demonstrate circuit operation on test chips fabricated using a 1.5 mum process. The experimental results indicate pulsewidths varying from about 900 ps to over 3 ns as the laser energy was increased

A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was considerably reduced, while simultaneously decreasing the lock-in time of the DPLL. The design results in a decreased area requirement with minimal impacts on phase jitter and power consumption. Furthermore, the design eliminates the charge pump as the most vulnerable module and significantly hardens the DPLL

Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells.

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

A radiation-hardened-by-design phase-locked loop (PLL)-designed and fabricated in 130 nm CMOS-is shown to mitigate single-event transients (SETs). Two-photon-absorption (TPA) laser tests were used to characterize the error signatures of the PLL and to perform single-event upset (SEU) mapping of the PLL sub-components. Results show that a custom, voltage-based charge pump reduces the error response of the PLL over conventional designs by more than two orders of magnitude as measured by the number of erroneous PLL clock pulses following a single-event. Additionally, SEU mapping indicates a 99% reduction in the vulnerable area of the radiation-hardened-by-design (RHBD) charge pump over a conventional design. Furthermore, the TPA experiments highlight the importance of the voltage-controlled oscillator in the overall SET response of the PLL implementing the RHBD charge pump.

Frequency domain analysis of analog single-event transients in linear circuits

Using frequency-domain analysis techniques, a study of the relationship between the frequency spectrum of a single-event transient (SET) stimulus and the frequency response of internal circuit blocks of typical operational amplifier architectures has been performed. Results explain several general analog SET (ASET) observations, including the relative importance of the stimulus temporal profile, the circuit bandwidth, and the ion strike location relative to major circuit modules. Benefits gained from frequency compensation are evident, as important filtering of high-frequency signal components occur, reducing detrimental effects on the operation of the circuit.

Total-dose and single-event effects in switching DC/DC power converters

Total-dose and single-event effects in discrete switching DC/DC power converters are examined using a combination of circuit measurements and simulations. The total-dose experiments focus on the response of the power MOSFET used as the switching element for the converters. The efficiencies of two different types of converters (boost and buck) degrade with increasing total dose, leading to eventual functional failure. The single-event transient response of the converters is determined by the response of the feedback control circuitry. Radiation response is studied using both electrical measurements and simulation techniques, and issues affecting circuit failure are identified.

Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

Voltage-controlled oscillators (VCOs) have been shown to dominate the single-event transient (SET) response of mixed-signal circuits such as the phase-locked loop (PLL). An analytical model is presented to determine the VCO design parameters and the associated SET vulnerability. Additionally, radiation-hardened-by-design (RHBD) techniques to mitigate SETs in current-starved VCOs are presented. The proposed mitigation techniques reduce the phase displacement in the output of the VCO following a single-event (SE) by approximately 66%. The availability of the analytical model and RHBD techniques will improve the SE performance of VCO and PLL designs to ensure a specified tolerance to SEs.

Effect of Transistor Density and Charge Sharing on Single-Event Transients in 90-nm Bulk CMOS

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width.

Total dose effects in a linear Voltage regulator

Experiments and simulations are used to analyze the total-dose response of a linear voltage regulator. Degradation of the dynamic output range of the error amplifier is determined to be responsible for the regulator failure. We present a first-order model to reproduce total dose circuit and system response. Modification of the bias circuitry in the error amplifier using beta compensation techniques is shown to harden the system to a significantly higher total dose level.