Cheong Min Hong

Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.

High Performance Nanocrystal Based Embedded Flash Microcontrollers with Exceptional Endurance and Nanocrystal Scaling Capability

In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has intrinsic capability of exceeding 500K program/erase cycles. We also show that the cycling performance across temperature (-40C to 125C) is very well behaved even while maintaining high performance that meets or exceeds the requirements of consumer, industrial, and automotive markets. In specific EEPROM implementation, such high endurance is capable of delivering in excess of 200M data updates. In addition, we also demonstrate that the nanocrystal flash memory is highly scalable to the next generation nodes and the scaling can be accomplished without degradation of pro-gram/erase speed, endurance and reliability.

16Mb Split Gate Flash Memory with Improved Process Window

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

Reliability Study of Split Gate Silicon Nanocrystal Flash EEPROM

In this paper, we present a measurement based on biased data retention to determine the direction of charge loss. Top oxide and bottom oxide thickness can be optimized to meet long term reliability goal. A split gate nanocrystal nonvolatile memory with large program window, while demonstrating excellent data retention and program disturb characteristics is also presented.

Optimization of 90nm Split Gate Nanocrystal Non-Volatile Memory

A 90 nm split gate nanocrystal bitcell has been demonstrated with scaled select gate oxide and adjustable control gate threshold voltage that allows for fast, low power SSI operation and top erase. This bitcell performance is excellent and holds promise for embedded flash applications.