Aseem Srivastava

II: Ultra-Shallow Junction Cleaning: Methodologies for Process and Chemistry Optimization

Ultra-Shallow Junction process requirements for the coming technology nodes place restrictions on cleaning and stripping chemistries. This is driven by the need for zero substrate loss (ZSL), combined with extremely low defect densities. At the same time increasing implant doses at lower energies, and shallower implants of multiple species, combine to make dry strip and clean a significant challenge.

Silicon loss metrology using synchrotron x‐ray reflectance and Bragg diffraction

We use synchrotron x‐ray reflectometry and Bragg diffraction to study silicon loss in the low temperature plasma oxidation of silicon‐on‐insulator (SOI) wafers. We show that Laue oscillations associated with the Si (004) Bragg peak give the number of Si (004) planes in the device layer to within an experimental error of 0.07 nm and that X‐ray reflectometry gives the total thickness of the device layer and the surface oxide to within 0.05 nm. We find that silicon loss in samples processed in two different plasma systems correspond to an increase in total thickness that is consistent with the formation of SiO2.

Effluent Management for Non-Oxidizing Plasma Strip Processes

This paper reports on the techniques employed to control the redeposition of the partially dissociated organic photoresist (PR) byproducts in advanced non-oxidizing strip processes developed to meet the PR removal requirements of future technology nodes. System features, such as the design of heated process chamber walls and an on-board, RF-based oxygen plasma effluent abatement system are described in detail. The performance of these features to prevent or eliminate hydrocarbon buildup and manage effluent with non-oxidizing strip processes is also presented and discussed.