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Ashwani Kumar Gupta

Intel

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Publication

Featured researches published by Ashwani Kumar Gupta.

Archive | 1998

Method and apparatus for implementing a set-associative branch target buffer

Bradley D. Hoyt; Glenn I. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1994

Method and apparatus for resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1997

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1996

Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system

Wen-Hann Wang; Konrad K. Lai; Gurbir Singh; Michael W. Rhodehamel; Nitin V. Sarangdhar; John M. Bauer; Mandar S. Joshi; Ashwani Kumar Gupta

Archive | 1994

Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions

Chan W. Lee; Gary L. Brown; Adrian Carbine; Ashwani Kumar Gupta

Archive | 1996

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1998

Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution

Andrew F. Glew; Ashwani Kumar Gupta

Archive | 1995

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Darrell D. Boggs; Robert P. Colwell; Michael A. Fetterman; Andrew F. Glew; Ashwani Kumar Gupta; Glenn J. Hinton; David B. Papworth

Archive | 1997

Computer system employing streaming buffer for instruction preetching

Glenn J. Hinton; Ashwani Kumar Gupta; Sunil Shenoy

Archive | 1997

Method and apparatus for implementing a branch target buffer in CISC processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

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Collaboration

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Glenn J. Hinton

Intel

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David B. Papworth

Intel

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Michael A. Fetterman

Intel

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Bradley D. Hoyt

Intel

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Subramanian Natarajan

Intel

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Sunil Shenoy

Intel

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Reynold V. D'Sa

Intel

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Chan W. Lee

Intel

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Sa Reynold V D

Intel

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Andrew F. Glew

Intel

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