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Bradley D. Hoyt

Intel

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Publication

Featured researches published by Bradley D. Hoyt.

Archive | 1998

Method and apparatus for implementing a set-associative branch target buffer

Bradley D. Hoyt; Glenn I. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1994

Method and apparatus for resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1997

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1995

Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history

Bradley D. Hoyt; Glenn J. Hinton; Andrew F. Glew; Subramanian Natarajan

Archive | 1996

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1996

Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions

Bradley D. Hoyt; Subramanian Natarajan

Archive | 1997

Method and apparatus for implementing a branch target buffer in CISC processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1997

Method and apparatus for a branch instruction pointer table

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Subramanian Natarajan; Reynold V. D'Sa

Archive | 1994

Implementing a branch target buffer in CISC processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Sa Reynold V D

Archive | 1994

Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue

Adrian Carbine; Gary L. Brown; Bradley D. Hoyt; Donald D. Parker; Rajesh Kumar

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Subramanian Natarajan

Intel

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Glenn J. Hinton

Intel

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David B. Papworth

Intel

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Ashwani Kumar Gupta

Intel

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Michael A. Fetterman

Intel

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Sunil Shenoy

Intel

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Reynold V. D'Sa

Intel

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Sa Reynold V D

Intel

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Andrew F. Glew

Intel

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Adrian Carbine

Intel

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