Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Reynold V. D'Sa is active.

Publication


Featured researches published by Reynold V. D'Sa.


IEEE Micro | 2014

Haswell: The Fourth-Generation Intel Core Processor

Per Hammarlund; Alberto J. Martinez; Atiq Bajwa; David L. Hill; Erik G. Hallnor; Hong Jiang; Martin G. Dixon; Michael N. Derr; Mikal C. Hunsaker; Rajesh Kumar; Randy B. Osborne; Ravi Rajwar; Ronak Singhal; Reynold V. D'Sa; Robert S. Chappell; Shiv Kaushik; Srinivas Chennupaty; Stephan J. Jourdan; Steve H. Gunther; Thomas A. Piazza; Ted Burton

Haswell, Intels fourth-generation core processor architecture, delivers a range of client parts, a converged core for the client and server, and technologies used across many products. It uses an optimized version of Intel 22-nm process technology. Haswell provides enhancements in power-performance efficiency, power management, form factor and cost, core and uncore microarchitecture, and the cores instruction set.


design automation conference | 2010

What will make your next design experience a much better one

Thomas Harms; Juan-Antonio Caraballo; Reynold V. D'Sa; Ruud A. Haring; Derek Urbaniak; Guntram Wolski; James You

Top designers and design engineering managers will present this wish list to make their next (or even current) design a much better design experience. They will not focus on pie-in-the-sky research topics, but describe down-to-earth challenges that designers face in getting their designs out the door. The panelists will use their data and experiences to substantiate their wish lists and address the main question: What needs to change in the design flows and design tools to improve Time-to-Market (TTM) and design quality?


Archive | 1998

Method and apparatus for implementing a set-associative branch target buffer

Bradley D. Hoyt; Glenn I. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa


Archive | 1994

Method and apparatus for resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa


Archive | 1997

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa


Archive | 2000

System and method of maintaining and utilizing multiple return stack buffers

Reynold V. D'Sa; Rebecca E. Hebda; Stavros Kalafatis; Alan B. Kyker; Robert B. Chaput


Archive | 1997

Trace branch prediction unit

Robert F. Krick; Chan Woo Lee; Reynold V. D'Sa


Archive | 1998

System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units

Reynold V. D'Sa; Alan B. Kyker; Gad Sheaffer; Gustavo P. Espinosa; Stavros Kalafatis; Rebecca E. Hebda


Archive | 1996

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa


Archive | 1997

Method and apparatus for implementing a branch target buffer in CISC processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Researchain Logo
Decentralizing Knowledge