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Sunil Shenoy

Intel

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Featured researches published by Sunil Shenoy.

high level design validation and test | 2009

Leadership Microprocessors: Validation, debug and test

Sunil Shenoy

I will discuss the use of high level design and abstraction for modeling, simulation and validation of leadership microprocessors, the challenges we have faced in this domain, our learnings and our vision and strategy for the future.

Archive | 1998

Method and apparatus for implementing a set-associative branch target buffer

Bradley D. Hoyt; Glenn I. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1994

Method and apparatus for resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1993

Apparatus and method for an instruction cache locking scheme

Scott Huck; Konrad K. Lai; Sunil Shenoy; Larry Smith

Archive | 1997

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1996

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1997

Computer system employing streaming buffer for instruction preetching

Glenn J. Hinton; Ashwani Kumar Gupta; Sunil Shenoy

Archive | 1993

Apparatus and method for partial execution blocking of instructions following a data cache miss

Sunil Shenoy; James W. Wong

Archive | 1997

Method and apparatus for implementing a branch target buffer in CISC processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1995

Method and apparatus for dynamically expanding the pipeline of a microprocessor

Jay Heeb; Sunil Shenoy; Jimmy Wong

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Ashwani Kumar Gupta

Intel

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Bradley D. Hoyt

Intel

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David B. Papworth

Intel

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Glenn J. Hinton

Intel

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Michael A. Fetterman

Intel

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Subramanian Natarajan

Intel

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Reynold V. D'Sa

Intel

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Sa Reynold V D

Intel

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Jay Heeb

Intel

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M. Vittal Kini

Intel

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