Asko Kananen

A QCIF Resolution Binary I/O CNN-UM Chip

In this paper is reported a Cellular Nonlinear Network Universal Machine realization where there are 176 × 144 active cells. The size of the network is the standardized QCIF video image format and the design is aimed to be used in segmenting video images in future video applications requiring very low bit-rate for image transmission. The achieved cell density is 3000 cells/mm2 with a 0.25 micron standard digital CMOS process. Different building blocks inside the cell are given in detail and also the other implemented circuitry is thoroughly discussed. The physical realization of the design is also reported.

CNN applications from the hardware point of view: video sequence segmentation

In this paper, the problems present in hardware implementations of cellular non-linear network (CNN) type parallel processors are discussed. Instead of designing a multipurpose processor, or even a full image size application specific parallel processor, we suggest a division of the processing task into categories depending on the cell dynamics and on the spread of the influence of a cell. In this way, drastic savings can be achieved in silicon size and in processing speed. As an example, we use a CNN algorithm that was designed for video image segmentation for object-based compression of video signal. We start with discussion of the problems related to implementation of the algorithm with current multipurpose processors. We then introduce hardware structures that can be used in obtaining certain functionalities. In the same section, we also deal with the division of the processing task. We also compare the introduced hardware solution for the algorithm with multipurpose processor structures in silicon size, power consumption and in processing speed. Copyright

An analog array processor hardware realization with multiple new features

This paper describes functionalities which will soon be available in an analog array processor. By developing dedicated calculation cores for different types of applications, the processor size can be kept small and therefore the achieved resolution is relatively high. The available features include weighted ranked order filtering, gray scale mathematical morphology, second neighbor direct interaction and different plasticity options for templates, where the previous results of the processing define the weights in the future steps. A linear filter capable of low pass filtering is also included. The resulting processing unit is viewed at block level and the characteristics of functional blocks are assessed in terms of estimations of power consumption, evaluation time, die area and accuracy.

A mixed-mode polynomial-type CNN for analysing brain electrical activity in epilepsy

In this paper, a mixed-mode polynomial-type cellular neural network (CNN) for analysing brain electrical activity in epilepsy is presented. The principles and design characteristics of this application are overviewed. The main difference of the requirements of this application compared to conventional CNN realizations is that in addition to linear, cells are also coupled with polynomial-type couplings. A mixed-mode CNN is shown to be suitable for the realization of a polynomial-type CNN in the brain electrical activity analysis application. In a mixed-mode CNN multiplication is done in analog domain, whereas the integration and storage are digital. Suitability of different integration methods for cell level realization are studied and cell and network level design of a mixed-mode CNN is described. First-, second- and third-order polynomial feedback terms are included in the cell and Heuns integration method is used. In order to reduce the cell count, the array is designed so that it can process input data that has been divided into blocks. The whole input data is stored in parallel with the cells so that all input/output operations during processing are local. Cell structure is shown along with register connections between edge cells of the network. Analog power consumption and computing speed are estimated by HSPICE simulations using 0.25 µm digital CMOS process parameters. The die area of a network with 2×72 cells with 36 layers in each was determined by drawing the layout. Copyright

A mixed-mode polynomial cellular array processor hardware realization

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm/sup 2/, 1.027 million transistor cellular array processor with 2/spl times/72 PUs and 36 layers of memory in each was manufactured using a 0.25-/spl mu/m digital CMOS process. The array processor can perform gray scale Heuns integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72/spl times/72 data while keeping all input-output operations during processing local. One complete Heuns iteration round takes 166.4 /spl mu/s and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.

Realization of couplings in a polynomial type mixed-mode CNN

In this paper realization of couplings between cells in a polynomial type mixed-mode cellular neural network (CNN) is analyzed. One quadrant operation is required from the analog multipliers and polynomial circuits because in a mixed-mode CNN extension to four quadrant operation can be done digitally. A one quadrant multiplier is analyzed and simulated with HSPICE. Furthermore, circuits for generating second and third order polynomial terms of cell output are analyzed and HSPICE simulations are shown.

A/D and D/A converters in a mixed-mode CNN

In this paper A/D and D/A converters in a mixed-mode cellular neural network (CNN) are analyzed. The choice of A/D converter type is discussed and design characteristics associated with A/D converter design for a mixed-mode CNN are overviewed. A current mode successive approximation type A/D converter suitable for use in a mixed-mode CNN cell is shown. A current mode D/A converter is also shown in block level.

A 48 by 48 CNN chip operating with B/W images

A new very simple cellular neural network universal machine structure is presented. By using a high gain unipolar sigmoid as the cell output nonlinearity the coefficient building blocks can be integrated with high density. The new design reaches cell density about 10 times larger than the previous ones. A 48/spl times/48 cell grid has been fabricated using a 0.5 /spl mu/m standard digital CMOS process. The cell structure is described and some system level measurement results are given.

MPEG-4 encoder architecture for a shape segmentation CNN chip

A core of a digital encoder architecture has been simulated to investigate the suitability of a proposed cellular nonlinear network (CNN) algorithm for the video coding standard MPEG-4. The shape segmentation was simulated along with shape-adaptive DCT, motion estimation and motion compensation. The algorithm is found to be very suitable for MPEG-4 arbitrary shape segmentation. To realize the algorithm QCIF-size implementations capable of low-power and real time segmentation have been done.

A 32 /spl times/ 32 cellular test chip targeting new functionalities

In this paper the design of a cellular computer with 32/spl times/32 cells is discussed by referencing to different points of alternatives for realizing massively parallel analogue processor arrays. The design is a combination of cellular nonlinear network type computing and an analog microprocessor. Motivations are given for the selected solutions that are used to implement a test chip with a resolution of 32/spl times/32 cells. Digital solutions are used in the 32/spl times/32 design to mitigate the effect of traditional bottlenecks in computing speed, namely analog weight programming and analog I/O. Furthermore, as A/D/A converters are included in each cell, alternative solutions for analog storage are highlighted.