Tsukasa Tokutomi

19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers

A hybrid storage architecture of ReRAM and TLC (3b/cell) NAND Flash with RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniques with minimal area overhead. The first three approaches, (i) flexible RRef (FR), (ii) adaptive asymmetric coding (AAC), and (iii) verify trials reduction (VTR), are applied to 50nm ReRAM to improve the bit-error rate (BER) by 69% and performance by 97%. Techniques (iv) balanced RAID-5/6 and (v) bits/cell optimization (BCO) are applied to 2Xnm TLC NAND to reduce the failure rate by 98% and extend the lifetime (write/erase (W/E) cycles) by >22×, respectively.

Advanced error prediction LDPC for high-speed reliable TLC nand-based SSDs

Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flashs capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower VTH margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved reliability for Multi-Level-Cell (MLC) NAND flash [4]. However, in EP-LDPC program disturb is not modeled, so precision is limited, especially in short data retention <; 2 days. Here, AEP-LDPC is proposed for TLC NAND flash. By considering effects of program disturb, data retention and floating-gate capacitive coupling, the most accurate SSDs can be realized, with high speed read capability. The SSDs data-retention time increases by more than 12x, decode iterations decrease 57% and acceptable TLC NAND BER increases by more than 2.8 ×.

7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage

An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic VTH optimization and auto data recovery reduce the NAND Flash bit-error rate (BER) by 80% and 18%, respectively. These techniques can be implemented in the SSD controller without circuit overhead. No modification is required to the TLC NAND flash.

System-level error correction by read-disturb error model of 1Xnm TLC NAND Flash memory for read-intensive enterprise solid-state drives (SSDs)

Read-disturb Modeled LDPC (RDM-LDPC) ECC is proposed. Conventional Advanced Error-Prediction LDPC (AEP-LDPC) [1] corrects data-retention errors of data-storage-purpose SSDs storing photos, movies, etc. but cannot correct read-disturb errors. For read-intensive computing-purpose enterprise SSDs, this paper analyzes the read-disturb errors, develops the error model of 1Xnm TLC NAND Flash memory and proposes ECC suitable for read-disturb errors. It is experimentally demonstrated that proposed RDM-LDPC extends the read cycle of SSDs by 5000-times.

Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers

Versatile Triple-Level-Cell (TLC) NAND flash memory control with Read Hot/Cold Migration, Read Voltage Control and Edge Word Line Protection is proposed for data center application SSDs. Measured errors decrease by 85% and measured acceptable read cycles increase by 6.7-times.

Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs)

This paper proposes highly reliable coding methods for applications in two extreme conditions. n-out-of-8 level cell (nLC) is proposed for archival applications which require significantly long data-retention time with small write/erase cycle. On the other hand, for applications with large write/erase cycle and short data-retention time (enterprise application, etc.), universal asymmetric coding (UAC) is proposed. nLC reduces the number of memory states to improve the reliability with low cost overhead. In 7LC, the bit-error rate (BER) reduction will be 79% after 1k-year data retention while seven memory states are efficiently used out of eight states. By considering nLC with error-correcting codes (ECCs), the optimum number of cell levels (n) can be determined to minimize the bit-cost with given acceptable data-retention time. In UAC, the coding method is changed according to the write/erase cycle and data-retention time to keep the BER low. As a result, BER is reduced by 52% at maximum, compared with the original random pattern.

Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage

This paper proposes design methodology for highly reliable, high performance ReRAM and 3-bit/cell multi-level cell (MLC) NAND flash solid-state storage. Six techniques, calibrated RRef (CR), flexible RRef (FR), adaptive asymmetric coding (AAC), verify trials reduction (VTR), bits/cell optimization (BCO), and balanced RAID-5/6 are proposed. CR, FR, AAC, and VTR are for ReRAM. CR and FR change the read-reference resistance (RRef) to reduce the BER. AAC first increases the population of Set and then Reset. The BER reduction with FR and AAC is 69 and 78% with 60 and 75% asymmetry, respectively. In VTR, by changing the number of acceptable bit-errors, the total Reset time is reduced by 97% at maximum with small ECC calculation overhead. The reliability of 3-bit/cell MLC NAND flash memory is improved by BCO and balanced RAID-5/6. BCO reallocates 3-bit/cell MLC to 2-bit/cell MLC and single-level cell (SLC) and the write/erase cycle increases by over 22-times. Balanced RAID-5/6 evenly allocates upper/middle/lower pages to a stripe to reduce the RAID failure rate by 98%.

17x Reliability Enhanced LDPC Code with Burst-Error Masking and High-Precision LLR for Highly Reliable Solid-State-Drives with TLC NAND Flash Memory

Highly reliable LDPC ECC is introduced to improve the reliability of solid-state drives (SSDs). Although conventional AEP-LDPC ECC [3] is 12x highly reliable than BCH ECC, its error-correction capability is degraded due to the burst-errors and inaccurate log- likelihood ratio (LLR). To improve the reliability of TLC NAND flash, this paper proposes the burst-error masking (BEM) and program-disturb merged LLR estimation (PMLE). The first proposal, BEM eliminates the burst- errors by recording the error-location to the table. The second proposal, PMLE calculates the ratio of program-disturb errors to data-retention errors. As a result, more precise LLR is obtained. By combining BEM and PMLE, the SSD lifetime is extended by 17x and the table size overhead is reduced by 81%.

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

NAND flash memorys reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose–Chaudhuri–Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive V Ref shift (AVS) and V TH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (V Ref) based on temperature, W/E cycles and retention-time. AVS stores the optimal V Refs in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between V TH states. DVO reduces BER by 80%.