Atsushi Fujiwara

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time. >

A new testing acceleration chip for low-cost memory tests

It is argued that the development of semiconductor memories has reached a turning point. In the multimegabit dynamic random access memories (DRAMs) of the future, major factors contributing to the chip cost are process complexity, die size, equipment cost, and test cost. If conventional test methods are used, test costs will grow at an especially rapid rate. A memory test concept called the testing acceleration chip, which could reduce future test costs a hundredfold and yet maintain AC testing reliability, is presented.<<ETX>>

Capacitance coupled bus with negative delay circuit for high speed and low power (10 GB/s<500 mW) synchronous DRAMs

Capacitance coupled Bus (CcBus) with Negative Delay Circuit (NDC) architecture for high speed and low power Synchronous DRAMs (SDRAMs) has been developed. Data path power consumption is reduced to 1/5 (25mW@200MB/s). Transfer delay time is reduced to 1/2 (0.8 ns). High band width (10 GB/s) and low power (<500 mW) can be achieved. This 500 mW power consumption/package is an empirical value maintaining pause time in useful range. This architecture can keep Fill Frequencies (FF) in valuable region in Gbit-SDRAMs.