Tetsurou Matsumoto

A flexible redundancy technique for high-density DRAMs

The limitations of conventional redundancy techniques are pointed out and a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures. The proposed technique features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair. With this technique the yield improvement factor of 64-Mb DRAMs and beyond is estimated to be more than twice that with the conventional technique in the early stages of production. >

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage bouncings, temperature variation, and threshold-voltage deviation due to the process fluctuation, while maintaining CMOS-DRAM process compatibility. Moreover, feedback-loop stability and frequency response are maintained by ensuring a phase margin of 55° at a unity-gain frequency of 10 MHz using compensation through zero insertion. Implementation of these new circuits in a 16-Mb CMOS DRAM is reported

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance

The advantage of BiCMOS technology over CMOS technology in terms of the access time and the power dissipation is demonstrated for a 1.3- mu m 1-Mb DRAM with a TTL (transistor-transistor logic) interface. Two key results are obtained. One is that a BiCMOS driver achieves a 23% lower delay time and 28% lower power dissipation compared with a CMOS driver. This is due to the inherently small input gate capacitance of the BiCMOS inverter and the small number of inverter stages required to make the BiCMOS driver. The other result is that a 1-Mb BiCMOS DRAM incorporating the BiCMOS driver provides higher performance in terms of a 36% faster access time and 24% lower power dissipation after fabrication process deviations and temperature changes. The resistance to the process deviations and temperature changes of the BiCMOS is responsible for such excellent performance. >

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test

The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within +or-0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to +or-50 mV at an ambient temperature up to 120 degrees C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures. >