Osamu Hirabayashi

A process-variation-tolerant dual-power-supply SRAM with 0.179µm 2 Cell in 40nm CMOS using level-programmable wordline driver

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.

A 0.7 V Single-Supply SRAM With 0.495

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.

\mu

A single-power supply 64 kB SRAM is fabricated in a 45 nm bulk CMOS technology. The SRAM operates at 1GHz with a 0.7 V supply using a fine-grained bitline segmentation architecture and with an asymmetrical unit-ratio 6T cell. With the asymmetrical cell, 22% cell area has been saved compared to a conventional symmetrical cell. This bulk SRAM is designed for GHz-class sub-lV operation.

m

This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

^{2}

The growth of mobile equipment market is spurring demand for low-power SRAM macros. For mobile applications, in particular, there is a need to reduce standby current leakage while keeping memory cell data. For this purpose, several techniques have been reported. They introduce reduction of cell bias voltage in standby state, but the cell bias level is determined by Vth and supply voltage as described later. In 90nm technology and beyond, fluctuation of Vth is increasing and leakage reduction efficiency of these techniques is greatly affected. Therefore, a cell leakage reduction technique immune to process and/or environment fluctuations is required. In addition, leakage reduction in row decoder circuit is also desirable, because standby current leakage in peripheral circuits is dominated by row decoders. In order to meet these requirements, a novel cell bias control technique and a novel row decoder circuit are proposed. We fabricated a 90nm 512Kb low leakage SRAM macro.

Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme.

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation.

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm 2 cell in 32nm high- k metal-gate CMOS

A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.

A low leakage SRAM macro with replica cell biasing scheme

DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a Hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90nm technology.

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Design-for-test (DFT) techniques for acquiring at-speed function fail bit maps with conventional wafer test equipment are proposed. The SRAM core is operated with a high frequency clock generated by a gain-suppressed VCO which can reduce clock jitter. The data are output with a data out strobe control circuit synchronizing with an external low frequency clock. Using these techniques, the SRAM chip appears to be operating with a low frequency tester clock while the SRAM core is operated with a high frequency internal clock. Therefore, a fail bit map at high frequency operation can be obtained with conventional wafer test equipment. The at-speed test with fail bit map acquisition allows slow bit cell replacement to spare cell or chip-by-chip internal timing optimization with fuse-blowing. It results in a drastic reduction in test cost and performance yield improvement.