Yasuhisa Takeyama

A process-variation-tolerant dual-power-supply SRAM with 0.179µm 2 Cell in 40nm CMOS using level-programmable wordline driver

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.

A 0.7 V Single-Supply SRAM With 0.495

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.

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Today NAND Flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. Figure 13.6.1 shows the memory-density trend since 2003. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2b/cell MLC technology was introduced. Recently, MLC NAND flash memories with more than 2b/cell [1,2] have been reported.

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A single-power supply 64 kB SRAM is fabricated in a 45 nm bulk CMOS technology. The SRAM operates at 1GHz with a 0.7 V supply using a fine-grained bitline segmentation architecture and with an asymmetrical unit-ratio 6T cell. With the asymmetrical cell, 22% cell area has been saved compared to a conventional symmetrical cell. This bulk SRAM is designed for GHz-class sub-lV operation.

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This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

The growth of mobile equipment market is spurring demand for low-power SRAM macros. For mobile applications, in particular, there is a need to reduce standby current leakage while keeping memory cell data. For this purpose, several techniques have been reported. They introduce reduction of cell bias voltage in standby state, but the cell bias level is determined by Vth and supply voltage as described later. In 90nm technology and beyond, fluctuation of Vth is increasing and leakage reduction efficiency of these techniques is greatly affected. Therefore, a cell leakage reduction technique immune to process and/or environment fluctuations is required. In addition, leakage reduction in row decoder circuit is also desirable, because standby current leakage in peripheral circuits is dominated by row decoders. In order to meet these requirements, a novel cell bias control technique and a novel row decoder circuit are proposed. We fabricated a 90nm 512Kb low leakage SRAM macro.

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme.

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation.

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm 2 cell in 32nm high- k metal-gate CMOS

A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.

A low leakage SRAM macro with replica cell biasing scheme

Battery lifetime is the key feature in the growing markets of sensor networks and energy-management system (EMS). Low-power MCUs are widely used in these systems. For these applications, standby power, as well as active power, is important contributor to the total energy consumption because active sensing or computing phases are much shorter than the standby state. Figure 13.4.1 shows a typical power profile of low-power MCU applications. To achieve many years of battery lifetime, the power consumption of the chip must be kept below 1μA during deep sleep mode. Another key feature of a low-power MCU for such applications is fast wake-up from deep-sleep mode, which is important for low application latency and to keep wake-up energy minimal. For fast wake-up, the system must retain its state and logged information during sleep mode because several-hundred microseconds are needed for reloading such data to memories. Conventional SRAM consumes much higher retention current than the required deep-sleep-mode current as shown in Fig. 13.4.1. Embedded Flash memories have limited write endurance on the order of 105 cycles making them difficult to use in applications that frequently power down. Embedded FRAM [1,2] has been used for this purpose and it could be used as a random-access memory as well as a nonvolatile memory. However, as a random-access memory, its slow operation and high energy consumption [1,2] limits performance of the MCU and battery lifetime. Furthermore, additional process steps for fabricating FRAM memory cells increase the cost of MCU. SRAM can operate at higher speed with lower energy without additional process steps, but high retention current makes it difficult to sustain data in deep-sleep mode. To solve this problem, we develop low-leakage current SRAM (XLL SRAM) that reduce retention current by 1000× compared to conventional SRAM and operate with less than 10ns access time. The retention current of XLL SRAM is negligible in the deep-sleep mode because it is much smaller than the amount of the deep-sleep-mode current of MCU, which is dominated by active current of the real-time clock and control logic circuits. By using XLL SRAM, the store and reload process during mode transitions can be eliminated and wake-up time from deep-sleep mode of MCU is reduced to few microseconds. This paper describes a 128kb SRAM with 3.5nA (27fA/b) retention current, 7ns access time, and 25μW/MHz active energy consumption. Its low retention current, high-speed, and low-power operation enable to activate SRAM in the deep-sleep mode, and also provides fast wake-up, low active energy consumption and high performance to MCU.