Keiichi Kushida

A process-variation-tolerant dual-power-supply SRAM with 0.179µm 2 Cell in 40nm CMOS using level-programmable wordline driver

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.

A 0.7 V Single-Supply SRAM With 0.495

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.

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A single-power supply 64 kB SRAM is fabricated in a 45 nm bulk CMOS technology. The SRAM operates at 1GHz with a 0.7 V supply using a fine-grained bitline segmentation architecture and with an asymmetrical unit-ratio 6T cell. With the asymmetrical cell, 22% cell area has been saved compared to a conventional symmetrical cell. This bulk SRAM is designed for GHz-class sub-lV operation.

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Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.

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This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

The growth of mobile equipment market is spurring demand for low-power SRAM macros. For mobile applications, in particular, there is a need to reduce standby current leakage while keeping memory cell data. For this purpose, several techniques have been reported. They introduce reduction of cell bias voltage in standby state, but the cell bias level is determined by Vth and supply voltage as described later. In 90nm technology and beyond, fluctuation of Vth is increasing and leakage reduction efficiency of these techniques is greatly affected. Therefore, a cell leakage reduction technique immune to process and/or environment fluctuations is required. In addition, leakage reduction in row decoder circuit is also desirable, because standby current leakage in peripheral circuits is dominated by row decoders. In order to meet these requirements, a novel cell bias control technique and a novel row decoder circuit are proposed. We fabricated a 90nm 512Kb low leakage SRAM macro.

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme.

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

A power reduction technique is proposed for SRAM macros in which dual power supply scheme is combined with dynamic voltage scaling scheme. The test chip with 1Mb SRAM macro fabricated using 65nm CMOS process has demonstrated that the active power in low power mode is reduced by 25% compared to that of the conventional scheme. The leakage current at sleep mode is also decreased by three orders of magnitude compared to that of the conventional one.

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm 2 cell in 32nm high- k metal-gate CMOS

A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation.

A low leakage SRAM macro with replica cell biasing scheme

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, there have been two serious issues on the cache memories. One issue is large leakage power of SRAM-based cache (Ex. About 80% of average processor power in a mobile usage case [1]). Another one is large memory area of SRAM especially for last level cache (LLC) like L4 cache. Recently, eDRAM is used to reduce memory area for LLC (Fig. 1). However, gate length of eDRAM is difficult to be reduced less than 40-50 nm, and its power is not small due to frequent refresh (retention time ~ 100μs.). To reduce the cache power and decrease memory area further at the same time, advanced STT-MRAM based cache has been considered promising from theoretical analysis [2]. However, both low power and high density LLC have not been ever clarified based on a realistic MTJ (magnetic tunneling junction) integration and circuit design. This paper presents solutions for the power and memory density with more advanced STT-MRAM cell technologies by low-temperature process development and novel cache memory architecture based circuit design.