Yusuke Niki

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm 2 cell in 32nm high- k metal-gate CMOS

This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme.

A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs

A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction

The transistor variability deteriorates the energy consumption in SRAM. Especially it increases the energy consumed at the bitlines, which is the major portion of the total energy. The influence of the variation is enhanced at lower supply voltage, thus the voltage reduction sometimes degrades the energy efficiency. In this paper, we present circuit techniques that can reduce the SRAM energy consumption without the supply voltage scaling. An energy-efficient hierarchical bitline scheme can save energy consumption used for the bitline precharge. An energy-efficient offset-cancelling circuit and a process-variability-robust timing-generating circuit are also proposed.

A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access

A low power SRAM operating at the logic supply voltage of 0.5V-1.0V without chip by chip trimming has been developed. A Dynamic Cell Stability Monitor controls wordline level adaptively by sensing the data flip in reference memory cells. The cell failure rate in every process corner is improved. A Modulated Wordline Level Scheme for Replica Cell optimizes sense timing and the operating frequency is improved by 18% at 1.0V. A Multiple Memory Cell Access Mode pushes the minimum operating cell supply voltage down to 0.5V. A 40nm 2Mb SRAM test chip with 0.24um2 cell has demonstrated 0.5V operation.

A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme.

A supply-noise-rejection technique in ADPLL with noise-cancelling current source

We propose a supply noise rejection technique, which is applied to an all-digital phase-locked loop (ADPLL). Supply noise is cancelled by adding a cancellation current whose fluctuation is the same as that of a supply-noise component in an oscillator current. The proposed technique is realized with a small area and current dissipation, and is tolerant to process, voltage, and temperature (PVT) variations without calibration. The proof-of-concept chip was fabricated using a 65 nm CMOS technology. It was measured that the peak-to-peak jitter was reduced by 54 % in the presence of 30 mVpp, 15 MHz supply noise, and the robustness of the proposed technique was verified by the measurements.

A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.